Patents by Inventor Mitchell C. Taylor
Mitchell C. Taylor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8999798Abstract: NMOS transistors having controlled channel strain and junction resistance and methods for the fabrication of same are provided herein. In some embodiments, a method for forming an NMOS transistor may include (a) providing a substrate having a p-type silicon region; (b) depositing a silicon seed layer atop the p-type silicon region; (c) depositing a silicon-containing bulk layer comprising silicon, silicon and a lattice adjusting element or silicon and an n-type dopant atop the silicon seed layer; (d) implanting at least one of the lattice adjusting element or the n-type dopant which is absent from the silicon-containing bulk layer deposited in (c) into the silicon-containing bulk layer; and (e) annealing the silicon-containing bulk layer with an energy beam after implantation in (d). In some embodiments, the substrate may comprise a partially fabricated NMOS transistor device having a source/drain region defined therein.Type: GrantFiled: December 15, 2010Date of Patent: April 7, 2015Assignee: Applied Materials, Inc.Inventors: Mitchell C. Taylor, Susan B. Felch
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Publication number: 20110175140Abstract: NMOS transistors having controlled channel strain and junction resistance and methods for the fabrication of same are provided herein. In some embodiments, a method for forming an NMOS transistor may include (a) providing a substrate having a p-type silicon region; (b) depositing a silicon seed layer atop the p-type silicon region; (c) depositing a silicon-containing bulk layer comprising silicon, silicon and a lattice adjusting element or silicon and an n-type dopant atop the silicon seed layer; (d) implanting at least one of the lattice adjusting element or the n-type dopant which is absent from the silicon-containing bulk layer deposited in (c) into the silicon-containing bulk layer; and (e) annealing the silicon-containing bulk layer with an energy beam after implantation in (d). In some embodiments, the substrate may comprise a partially fabricated NMOS transistor device having a source/drain region defined therein.Type: ApplicationFiled: December 15, 2010Publication date: July 21, 2011Applicant: APPLIED MATERIALS, INC.Inventors: MITCHELL C. TAYLOR, SUSAN B. FELCH
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Patent number: 7671358Abstract: A transistor device having a conformal depth of impurities implanted by isotropic ion implantation into etched junction recesses. For example, a conformal depth of arsenic impurities and/or carbon impurities may be implanted by plasma immersion ion implantation in junction recesses to reduce boron diffusion and current leakage from boron doped junction region material deposited in the junction recesses. This may be accomplished by removing, such as by etching, portions of a substrate adjacent to a gate electrode to form junction recesses. The junction recesses may then be conformally implanted with a depth of arsenic and carbon impurities using plasma immersion ion implantation. After impurity implantation, boron doped silicon germanium can be formed in the junction recesses.Type: GrantFiled: September 4, 2007Date of Patent: March 2, 2010Assignee: Intel CorporationInventors: Nick Lindert, Mitchell C. Taylor
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Publication number: 20090142875Abstract: A method for forming a selective emitter on a silicon solar cell is provided including forming an oxide layer on a surface of the P-type silicon substrate, implanting phosphorus doping atoms into the oxide layer on the substrate using plasma immersion ion implantation, patterning the oxide layer, annealing the substrate to provide heavily doped regions in the patterned regions and a lightly doped region between the patterned regions, and providing metal contacts to the heavily doped regions.Type: ApplicationFiled: November 30, 2007Publication date: June 4, 2009Applicant: APPLIED MATERIALS, INC.Inventors: Peter Borden, Mitchell C. Taylor
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Publication number: 20080160683Abstract: A method including implanting carbon and fluorine into a substrate in an area of the substrate between a source/drain region and a channel, the area designated for a source/drain extension; and a source/drain extension dopant following implanting carbon and fluorine, implanting phosphorous in the area. A method including disrupting a crystal lattice of a semiconductor substrate in an area of the substrate between a source/drain region and a channel designated for a source/drain extension; after disrupting, implanting carbon and fluorine in the area; and implanting phosphorous in the area. A method including performing a boron halo implant before implanting phosphorous to form N-type source/drain extensions. An apparatus including an N-type transistor having a source/drain extension comprising carbon and phosphorous, formed in an area of a substrate between a source/drain region of the transistor and a channel of the transistor.Type: ApplicationFiled: December 29, 2006Publication date: July 3, 2008Inventors: Aaron O. Vanderpool, Mitchell C. Taylor
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Patent number: 7314804Abstract: A transistor device having a conformal depth of impurities implanted by isotropic ion implantation into etched junction recesses. For example, a conformal depth of arsenic impurities and/or carbon impurities may be implanted by plasma immersion ion implantation in junction recesses to reduce boron diffusion and current leakage from boron doped junction region material deposited in the junction recesses. This may be accomplished by removing, such as by etching, portions of a substrate adjacent to a gate electrode to form junction recesses. The junction recesses may then be conformally implanted with a depth of arsenic and carbon impurities using plasma immersion ion implantation. After impurity implantation, boron doped silicon germanium can be formed in the junction recesses.Type: GrantFiled: January 4, 2005Date of Patent: January 1, 2008Assignee: Intel CorporationInventors: Nick Lindert, Mitchell C. Taylor
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Patent number: 7235843Abstract: The use of a carbon implant, in addition to the conventional fluorine implant, may significantly reduce the transient enhanced diffusion in P-type source drain extension regions. As a result, resistivity may be reduced, and dopant density may be increased, increasing current drive in some embodiments.Type: GrantFiled: January 5, 2006Date of Patent: June 26, 2007Assignee: Intel CorporationInventors: Aaron O. Vanderpool, Mitchell C. Taylor
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Patent number: 7052978Abstract: Arrangements incorporating laser-induced cleaving.Type: GrantFiled: August 28, 2003Date of Patent: May 30, 2006Assignee: Intel CorporationInventors: Mohamad A. Shaheen, Mark Y. Liu, Mitchell C. Taylor
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Patent number: 7015108Abstract: The use of a carbon implant, in addition to the conventional fluorine implant, may significantly reduce the transient enhanced diffusion in P-type source drain extension regions. As a result, resistivity may be reduced, and dopant density may be increased, increasing current drive in some embodiments.Type: GrantFiled: February 26, 2004Date of Patent: March 21, 2006Assignee: Intel CorporationInventors: Aaron O. Vanderpool, Mitchell C. Taylor
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Patent number: 6936518Abstract: A polysilicon structure may be defined on a semiconductor substrate using plasma doping to dope the sidewalls and upper surface of the polysilicon material as well as the source drain extensions. Shortly after plasma doping, the structure may be encapsulated within a suitable capping layer to prevent the removal of the thin surface doped regions during subsequent semiconductor processing.Type: GrantFiled: January 21, 2004Date of Patent: August 30, 2005Assignee: Intel CorporationInventors: Jack Hwang, Mitchell C. Taylor, Mark Y. Liu, Nick Lindert
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Patent number: 6794755Abstract: Described is a method and apparatus for altering the top surface of a metal interconnect. In one embodiment of the invention, a metal interconnect and a barrier layer are formed into an interlayer dielectric (ILD) and the metal interconnect and the barrier layer are planarized to the top of the ILD. The top surfaces of the metal interconnect, the barrier layer, and the ILD are altered with a second metal to form an electromigration barrier. In one embodiment of the invention, the second metal is prevented from contaminating the electrical resistivity of the metal interconnect.Type: GrantFiled: March 25, 2003Date of Patent: September 21, 2004Assignee: Intel CorporationInventors: Jose A. Maiz, Xiaorong Morrow, Thomas Marieb, Carolyn Block, Jihperng Leu, Paul McGregor, Markus Kuhn, Mitchell C. Taylor
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Publication number: 20040056329Abstract: Described is a method and apparatus for altering the top surface of a metal interconnect. In one embodiment of the invention, a metal interconnect and a barrier layer are formed into an interlaver dielectric (ILD) and the metal interconnect and the barrier layer are planarized to the top of the ILD. The top surfaces of the metal interconnect, the barrier layer, and the ILD are altered with a second metal to form an electromigration barrier. In one embodiment of the invention, the second metal is prevented from contaminating the electrical resistivity of the metal interconnect.Type: ApplicationFiled: March 25, 2003Publication date: March 25, 2004Inventors: Jose A. Maiz, Xiaorong Morrow, Thomas Marieb, Carolyn Block, Jihperng Leu, Paul McGregor, Markus Kuhn, Mitchell C. Taylor
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Publication number: 20040056366Abstract: Described is a method and apparatus for altering the top surface of a metal interconnect. In one embodiment of the invention, a metal interconnect and a barrier layer are formed into an interlayer dielectric (ILD) and the metal interconnect and the barrier layer are planarized to the top of the ILD. The top surfaces of the metal interconnect, the barrier layer, and the ILD are altered with a second metal to form an electromigration barrier. In one embodiment of the invention, the second metal is prevented from contaminating the electrical resistivity of the metal interconnect.Type: ApplicationFiled: September 25, 2002Publication date: March 25, 2004Inventors: Jose A. Maiz, Xiaorong Morrow, Thomas Marieb, Carolyn Block, Jihperng Leu, Paul McGregor, Markus Kuhn, Mitchell C. Taylor
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Patent number: 6590271Abstract: A shallow trench isolation (STI) structure is formed by etching trenches into the surface of a substrate in alignment with a patterned masking layer. An ion implantation of, for example, carbon, nitrogen, or oxygen, is performed so as to create an electrically insulating layer extending downwardly from a bottom surface of the trench. By implanting such extensions, STI structures with greater effective aspect ratios may be obtained which, in turn, allow greater packing density in integrated circuits. Implanted isolation structures may be formed without etching a trench by implanting into regions of the substrate. In this way, trench etch, dielectric back-fill, and planarization operations can be eliminated. Furthermore the implanted regions may be formed by multiple implants at different energies so as to obtain multiple, typically contiguous, target ranges.Type: GrantFiled: August 24, 2001Date of Patent: July 8, 2003Assignee: Intel CorporationInventors: Mark Y. Liu, Leonard C. Pipes, Mitchell C. Taylor
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Publication number: 20020197885Abstract: A method described for making a semiconductor transistor having a thin gate dielectric layer with a high k-value but without any impurities in a channel in silicon directly below the gate dielectric layer. An apparatus is used which pulses a cathode to create a plasma generating voltage potential between the cathode and an anode provided by a wall of a chamber of the apparatus. The plasma generating voltage generates an ion plasma out of a gas in the chamber. The ion plasma is maintained transient which allows for better control of its energy. A portion of a wafer stand is pulsed with a small voltage which extracts and accelerates ions out of the plasma into a silicon dioxide gate dielectric layer formed on a wafer in the chamber.Type: ApplicationFiled: June 22, 2001Publication date: December 26, 2002Inventors: Jack Hwang, Mitchell C. Taylor
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Patent number: 6432798Abstract: A shallow trench isolation (STI) structure is formed by etching trenches into the surface of a substrate in alignment with a patterned masking layer. An ion implantation of, for example, carbon, nitrogen, or oxygen, is performed so as to create an electrically insulating layer extending downwardly from a bottom surface of the trench. By implanting such extensions, STI structures with greater effective aspect ratios may be obtained which, in turn, allow greater packing density in integrated circuits. Implanted isolation structures may be formed without etching a trench by implanting into regions of the substrate. In this way, trench etch, dielectric back-fill, and planarization operations can be eliminated. Furthermore the implanted regions may be formed by multiple implants at different energies so as to obtain multiple, typically contiguous, target ranges.Type: GrantFiled: August 10, 2000Date of Patent: August 13, 2002Assignee: Intel CorporationInventors: Mark Y. Liu, Leonard C. Pipes, Mitchell C. Taylor
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Publication number: 20020086502Abstract: A method of forming a doped region. According to the present invention ions are implanted into a semiconductor material. The ion implanted semiconductor material is then laser annealed to form a doped semiconductor region.Type: ApplicationFiled: December 29, 2000Publication date: July 4, 2002Inventors: Mark Y. Liu, Mitchell C. Taylor, Shaofeng Yu
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Publication number: 20020037627Abstract: A shallow trench isolation (STI) structure is formed by etching trenches into the surface of a substrate in alignment with a patterned masking layer. An ion implantation of, for example, carbon, nitrogen, or oxygen, is performed so as to create an electrically insulating layer extending downwardly from a bottom surface of the trench. By implanting such extensions, STI structures with greater effective aspect ratios may be obtained which, in turn, allow greater packing density in integrated circuits. Implanted isolation structures may be formed without etching a trench by implanting into regions of the substrate. In this way, trench etch, dielectric back-fill, and planarization operations can be eliminated. Furthermore the implanted regions may be formed by multiple implants at different energies so as to obtain multiple, typically contiguous, target ranges.Type: ApplicationFiled: August 24, 2001Publication date: March 28, 2002Inventors: Mark Y. Liu, Leonard C. Pipes, Mitchell C. Taylor
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Patent number: 6200883Abstract: In ion implantation processes for forming junctions in semiconductor devices, a proportion of ions implant into the semiconductor material beyond the desired junction depth due to channelling along axes and planes of symmetry in the crystal. A method is provided in which ions are implanted at a series of different energies starting with a lower energy than that required for the desired junction depth. The initial amorphising of the surface regions of the semiconductor during the lower energy implantation reduces the channelling probability when the ions are subsequently implanted at the full energy resulting in a more sharply defined junction.Type: GrantFiled: June 16, 1997Date of Patent: March 13, 2001Assignee: Applied Materials, Inc.Inventors: Mitchell C. Taylor, Babak Adibi, Majeed Ali Foad
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Patent number: 6198142Abstract: A novel MOS transistor having minimal junction capacitance in this method of fabrication. According to the present invention, a gate dielectric layer is formed on a first surface of the semiconductor substrate. A gate electrode is then formed on the gate dielectric layer. Next, a pair of recesses are formed in the semiconductor substrate on opposite sides of the gate electrode. A dielectric layer is then formed on the surface of each of the recesses. A Semiconductor material is then deposited into the recesses to form a pair of source/drain regions.Type: GrantFiled: July 31, 1998Date of Patent: March 6, 2001Assignee: Intel CorporationInventors: Robert S. Chau, Chia-Hong Jan, Paul Packan, Mitchell C. Taylor