Patents by Inventor Mitchell C. Taylor

Mitchell C. Taylor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of fabricating a MOS transistor with a raised source/drain extension
    Patent number: 6121100
    Abstract: A method of forming a MOS transistor. According to the method of the present invention, a pair of source/drain contact regions are formed on opposite sides of a gate electrode. After forming the pair of source/drain contact regions, semiconductor material is deposited onto opposite sides of the gate electrode. Dopants are then diffused from the semiconductor material into the substrate beneath the gate electrode to form a pair of source/drain extensions.
    Type: Grant
    Filed: December 31, 1997
    Date of Patent: September 19, 2000
    Assignee: Intel Corporation
    Inventors: Ebrahim Andideh, Lawrence Brigham, Robert S. Chau, Tahir Ghani, Chia-Hong Jan, Justin Sandford, Mitchell C. Taylor
  • Ion implanter with post mass selection deceleration
    Patent number: 5932882
    Abstract: A decel lens assembly (9) located between the mass selection flight tube and the substrate holder comprises a first electrode (65) at the substrate potential, a second electrode (60) at the flight tube potential and a field electrode (61) between the two at a negative potential to provide focusing. The axial spacing in the beam direction between the first and second electrodes is less than the smallest transverse dimension of the field electrode. The decel lens assembly (9) is mounted directly opposite the outlet from the process chamber to the vacuum pump to maximize evacuation efficiency. An additional screening electrode (56) is provided between the second electrode of the decel lens assembly and the exit aperture of the mass selector. A perforated screening cylinder (54) is mounted on the light tube with the second electrode of the lens assembly mounted at the down beam end of the cylinder. A first electrode has a cylindrical screening flange extending around the field electrode.
    Type: Grant
    Filed: September 8, 1997
    Date of Patent: August 3, 1999
    Assignee: Applied Materials, Inc.
    Inventors: Jonathan Gerald England, Babak Adibi, Mitchell C. Taylor
  • Method of forming a transistor
    Patent number: 5908313
    Abstract: A novel MOS transistor having minimal junction capacitance in this method of fabrication. According to the present invention, a gate dielectric layer is formed on a first surface of the semiconductor substrate. A gate electrode is then formed on the gate dielectric layer. Next, a pair of recesses are formed in the semiconductor substrate on opposite sides of the gate electrode. A dielectric layer is then formed on the surface of each of the recesses. A Semiconductor material is then deposited into the recesses to form a pair of source/drain regions.
    Type: Grant
    Filed: December 31, 1996
    Date of Patent: June 1, 1999
    Assignee: Intel Corporation
    Inventors: Robert S. Chau, Chia-Hong Jan, Paul Packan, Mitchell C. Taylor