Abstract: According to one embodiment, a battery includes a container, an electrode group, an electrolytic solution, a sealing plate, a terminal, an injecting port, a sealing plug, a lead and a pressing member. The injecting port is opened in the sealing plate. The sealing plug closes the injecting port of the sealing plate, and is made of an elastic material. The lead electrically connects a positive electrode or a negative electrode of the electrode group to the terminal. The pressing member is integrated with the lead. The pressing member presses the sealing plug to the sealing plate.

Abstract: According to one embodiment, a battery includes a container, an electrode group, an electrolytic solution, a sealing plate, a terminal, an injecting port, a sealing plug, a lead and a pressing member. The injecting port is opened in the sealing plate. The sealing plug closes the injecting port of the sealing plate, and is made of an elastic material. The lead electrically connects a positive electrode or a negative electrode of the electrode group to the terminal. The pressing member is integrated with the lead. The pressing member presses the sealing plug to the sealing plate.

Abstract: A semiconductor device which achieves high-speed access and prevents the latch-up for any power inputting sequence by a plurality of power sources is disclosed. Where the chip voltage VDD is earlier inputted, an N well bias circuit 9 and a P well bias circuit 10 are activated, and an N-type well 12 and a P-type well 13 are biased respectively. After that, although the interface voltage VDDQ is inputted, the latch-up is not generated. On the other hand, where the interface voltage VDDQ is earlier inputted to a terminal 8, the N well bias circuit 9 and the P well bias circuit 10 are activated through a bypass circuit 15, and the N-type well 12 and the P-type well 13 are biased. Accordingly, although the chip voltage VDD is inputted after that, the latch-up is not generated.

Abstract: Process information obtained by a process section is input to a host computer. The process information includes information about a film, information about etching, information about cleaning, information about heat treatment, and information about a test. Yield information obtained by a D/S section is also input to the host computer. The host computer classifies wafers or lots into a plurality of quality ranks on the basis of these pieces of information, and supplies process conditions determined on the basis of the quality ranks to a burn-in section and a test section. The burn-in section and the test section respectively execute screening tests on the basis of the process conditions.

Abstract: A method of producing a semiconductor device of high integration density and high reliability with high yield, using self-alignment techniques, including forming a gate electrode on a semiconductor substrate of a first conductivity type with an insulating film arranged above and below it, forming a pair of first impurity regions of a second conductivity type mutually separated and self-aligned with the gate electrode in the substrate, forming a wall consisting of insulator on at least one side face of the gate electrode and the upper and lower insulating films, forming a second highly doped impurity region of second conductivity type at greater depth in the substrate than the first impurity region in a self-aligned manner with respect to the wall, forming an electrode layer connected to the second impurity region, with at least a portion of the electrode extending over the upper insulating film of the gate electrode, and selectively forming a wiring layer on the electrode layer.

Abstract: A novel semiconductor memory device having address comparator, word line drive circuit sense circuit, and control circuit is disclosed. The comparator judges whether or not a row address read in the present access cycle is in correspondence with that in the last cycle. Where it is judged that the former is not in correspondence with the latter, the control circuit allows the sense circuit to select a word line by this row address to transfer data of a memory cell to the bit line to allow the sense means to sense. On the other hand, where it is judged by the comparator that the former is in correspondence with the latter, since data of the memory cell belonging to the same word line is already sensed in the last cycle, the control circuit allows the readout circuit to read out data from a bit line corresponding to the column address without causing the sense circuit to carry out a sense operation for a second time.

Abstract: A method of producing a semiconductor device of high integration density and high reliability with high yield, using self-alignment techniques, including forming a gate electrode on a semiconductor substrate of a first conductivity type with an insulating film arranged above and below it, forming a pair of first impurity regions of a second conductivity type mutually separated and self-aligned with the gate electrode in the substrate, and forming a wall consisting of insulator on at least one side face of the gate electrode and the upper and lower insulating films, forming a second highly doped impurity region of second conductivity type at greater depth in the substrate than the first impurity region in a self-aligned manner with respect to the wall, forming an electrode layer connected to the second impurity region, with at least a portion of the electrode extending over the upper insulating film of the gate electrode, and selectively forming a wiring layer on the electrode layer.

Abstract: The semiconductor integrated circuit comprises a semiconductor substrate having a circuit region, a pad formed at the surface of the semiconductor substrate and forming a PN junction with the semiconductor substrate, and first and second electrodes. Each electrode contacts the semiconductor region such that the contacting regions of the electrodes face each other with a ring shaped region between.

Abstract: A dynamic random access memory system comprises first and second memory banks. A plurality of memory cells connected to a word line are grouped into first and second groups. The first group is arranged in the first memory bank and the second group is arranged in the second memory bank. Read/write means is provided in which each n bits from and to the first group and each n bits from and to the second group are read and written alternatively. Each bit is read and written in synchronism with the toggles of a column address strobe signal.

Abstract: A first semiconductor layer of a P.sup.+ type is formed on a semiconductor substrate of a P.sup.- type and a mask layer is formed on a portion of the first semiconductor layer other than that area where a capacitor is to be formed. A hole is formed in a direction of a thickness of the first semiconductor layer, using the mask layer. An N.sup.+ is formed on the inner surface of the hole with the mask layer as a mask. An insulating film for capacitor formation is formed on the inner surface of the resultant hole and on that atea of the first semiconductor layer where the resultant dynamic memory cell is electrically separated from an adjacent dynamic memory cell. A conductive layer acting as a capacitor electrode is formed on the capacitor formation insulating film. With the conductive layer as a mask, an impurity of an N type is doped into the first semiconductor layer to form a second semiconductor layer of a P.sup.- type in the surface portion of the first semiconductor layer.

Abstract: A semiconductor memory device having at least one memory cell array block with a plurality of memory cells formed at the surface of a semiconductor substrate. Each memory cell includes a transistor and memory capacitor. The device further has a plurality of word lines for addressing the memory cells, a plurality of bit lines for reading from and writing to the memory capacitors, at least one cell plate formed on the semiconductor substrate, the cell plate forming a common electrode of the memory capacitors, a cell plate voltage generator for supplying a voltage of a level between the supply voltage and the ground voltage to the cell plate, and a control circuit for controlling the output impedance of the cell plate voltage generating unit.

Abstract: A dynamic random access memory is disclosed which has memory cell units formed on a silicon substrate, each of which includes four memory cells, each of these including a MOS transistor and a MOS capacitor. One cell unit occupies a substantially square area of the surface of the substrate. The four memory cells included in this cell unit are arranged along the diagonal lines of the square area in the shape of a cross. The four transistors are connected to a common drain through a common drain region. The capacitors are respectively arranged at the four corners of the square area so as to have a relatively increased capacitor area, thereby obtaining a large capacitance.

Abstract: In a dynamic semiconductor memory, bit line pairs and word lines are perpendicular to each other and arranged in a matrix constituted by memory cells. Dummy cells are arranged at intersections between the bit line pairs and a pair of dummy cell word lines. The capacitance of each dummy cell is half that of the memory cell. A pre-sense amplifier and a main sense amplifier are arranged in each pair of bit lines. When data is read out from a selected memory cell, the pre-sense amplifiers are simultaneously activated to perform the pre-sensing operation. However, in the main sensing operation, only one specific main sense amplifier arranged in a certain bit line pair including the bit line connected to the selected memory cell is activated.

Abstract: A voltage applying circuit is adapted to a semiconductor memory device comprising a plurality of memory cells which each include MOS memory capacitors one terminal of each being connected to a common point. The output terminal of the voltage applying circuit is connected to the common point of the MOS capacitor, and a low voltage for normal operation of the MOS capacitor and a screening voltage for distinguishing a memory device, which is higher than that voltage, are selectively applied to the common connection point.

Abstract: In the semiconductor memory device of the invention, a normal voltage detecting circuit and a high voltage detecting circuit are connected to a terminal for the purpose of receiving a write enable signal. When a signal of normal level is supplied to the terminal, the circuit controls data read or write with respect to a memory cell array in accordance with the level of the write enable signal. An error correction code circuit is rendered operative, and a soft error generated in data read from the memory cell array is corrected. When a high voltage is applied to the terminal, the circuit sets the memory device in the read mode. The circuit detects application of the high voltage to the terminal and supplies a predetermined signal to an ECC control circuit. In response to the signal, the ECC control circuit stops the operation of the ECC circuit. Data without any correction of soft errors is output from the memory device, and testing of hard errors is simplified.

Abstract: A first semiconductor layer of a P.sup.+ type is formed on a semiconductor substrate of a P.sup.- type and a mask layer is formed on a portion of the first semiconductor layer other than that area where a capacitor is to be formed. A hole is formed in a direction of a thickness of the first semiconductor layer, using the mask layer. An N.sup.+ layer is formed on the inner surface of the hole with the mask layer as a mask. An insulating film for capacitor formation is formed on the inner surface of the resultant hole and on that area of the first semiconductor layer where the resultant dynamic memory cell is electrically separated from an adjacent dynamic memory cell. A conductive layer acting as a capacitor electrode is formed on the capacitor formation insulating film. With the conductive layer as a mask, an impurity of an N type is doped into the first semiconductor layer to form a second semiconductor layer of a P.sup.- type in the surface portion of the first semiconductor layer.

Abstract: A dynamic type semiconductor memory device having refreshing function includes a clock pulse generating circuit having a row clock pulse generating section which includes a plurality of cascade-connected delay circuits, a plurality of MOS transistors selectively connected between said delay circuits, and a gate control circuit for changing conduction resistances of the MOS transistors according to the level of a refreshing signal.

Abstract: A semiconductor memory device includes charge storage type memory cells, word lines and a bit line connected to the memory cells, a sense amplifier for detecting the memory data on the bit line, and a voltage push-up circuit for setting up a potential on the bit line. The voltage push-up circuit at first sets the potential on the bit line at a power supply voltage level after the memory data having a high logic level is detected by the sense amplifier, and then pushes up the potential on the bit line to a higher potential level than the power supply voltage.

Abstract: A MOS dynamic RAM consists of integrated memory cells each having a MOSFET and a MOS capacitor. The MOS dynamic RAM comprises a semiconductor substrate of a first conductivity type on which periodic projections and recesses are formed, a source region of a second conductivity type formed in the upper surface of each projection, a drain region of the second conductivity type formed in a bottom portion of each projection, a channel region of the first conductivity type sandwiched between the source and drain regions, a gate insulating film formed on a side wall of each projection between the source and drain regions, a gate electrode formed on the gate insulating film, a first insulating film formed on the source region, and a first electrode of the MOS capacitor formed on the first insulating film. The MOSFET is constituted by the source, drain and channel regions, the gate insulating film and the gate electrode.

Abstract: A MOS transistor integrated circuit device has at least one interconnection layer crossing the source and drain regions of a MOS transistor such that it overlies these source and drain regions. An electrical conductive layer is formed on the surface of at least one of the source and drain regions of the MOS transistor. The electrical conductive layer crosses the interconnection layer with an insulating layer therebetween such that it underlies the interconnection layer. The electrical conductive layer is separated from source and drain takeout electrodes and electrically insulated from the interconnection layer.