Abstract: A semiconductor device embodying this invention comprises a first conductive layer deposited on a semiconductor substrate to form a first element; a second conductive layer constituting a second element; and a third conductive layer superposed on the second conductive layer with an insulation layer interposed between said second and third conductive layers to form a third element. Only the second conductive layer formed from portions of the same layer of a conductive material is oxidized to provide an insulation layer; and consequently the first conductive layer is made thicker than the second conductive layer.

Abstract: The MOS dynamic memory cell comprises a first electroconductive layer formed on a surface of a first region of a semiconductor substrate having a first conductivity type and an impurity concentration of less than 5.times.10.sup.14 cm.sup.-3 through a first insulating film, a second semiconductor region having a higher impurity concentration than the first semiconductor region and provided adjacent to one end of the first semiconductor region, a second electroconductive layer formed on the second semiconductor region through a second insulating film, and a third semiconductor region of a second conductivity type and provided adjacent to the second semiconductor region. The second electroconductive layer is used as a row line, whereas the third semiconductor region is used as a column line as well as a digit line. An inversion layer is formed on a surface of the first semiconductor region. The MOS dynamic memory cell is used to fabricate a MOS dynamic random access memory.

Abstract: Disclosed is a semiconductor integrated circuit device, which comprises at least one selection circuit including a first node, a first MOS transistor for periodically pre-charging the first node, second MOS transistors for determining the potential state of the first node in response to a state designating signal, a third MOS transistor connected to the first node and functioning as a barrier, a second node connected through the barrier MOS transistor to the first node, a fourth MOS transistor for providing a signal at a level corresponding to the potential state of the second node, and a control circuit for holding the gate potential of the barrier MOS transistor at a low level for a period from the instant when the potential state of the first node is determined till the subsequent pre-charge cycle.

Abstract: A method for evaluating the measure precision of patterns such as photoresist and etched ones, and a photomask therefor. The photomask according to the present invention has a mask pattern corresponding to a pattern desired to be formed in a substrate, and also has a measure precision evaluating pattern formed at an area different from where the mask pattern is present. The measure precision evaluating pattern comprises a first measure precision evaluating pattern which has a plurality of pairs of pattern elements opposite to each other with a predetermined distance interposed therebetween, and a second measure precision evaluating pattern which has a plurality of pairs of pattern elements overlapped each other in a predetermined measure and arranged opposite to each other to form a constricted portion. The distance or the measure of overlapped area between paired pattern elements is varied with every pair of pattern elements.