Patents by Inventor Mitsugu Nagoya

Mitsugu Nagoya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7590916
    Abstract: A CRC value calculator enables throughput to be improved while keeping down the increase in the size of the circuitry. This is achieved by using (n+1) basic CRC circuits to configure a CRC value calculator in which the width of the data processed during one clock cycle is m2n bits. For example, when m2n bits is the data width processed per calculator cycle, the CRC value calculator of this invention is configured by using selectors to serially connect a CRC circuit that processes every m2n bits, a CRC circuit that processes every m2(n?1) bits, . . . , and a CRC circuit that processes every m20 bits. This configuration makes it possible to calculate a correct CRC value even when the remainder of an input network frame is not a multiple of m2n bits. Selectors are used to select CRC circuit output according to process data width. Reduction of the operating frequency is avoided by using registers to form a pipeline between CRC circuits.
    Type: Grant
    Filed: June 9, 2006
    Date of Patent: September 15, 2009
    Inventors: Toshihiro Katashita, Kenji Toda, Kazumi Sakamaki, Takeshi Inui, Tadamasa Takayama, Mitsugu Nagoya, Yasunori Terashima
  • Publication number: 20090216802
    Abstract: A data processing system includes a data processing unit which processes data acquired and a plurality of data retaining units which store databases used to process the data. Each of the plurality of data retaining units stores a primary database in common and stores the respective shares of a secondary database. The primary database stores a list of IDs for identifying data to be processed by any one of the plurality of data processing units. Each of the data processing units is notified of a range of IDs that the data processing unit handles, among the list of IDs stored in the primary database, and, when acquiring a packet containing an ID that lies within the range of IDs, the data processing unit processes the packet.
    Type: Application
    Filed: July 27, 2006
    Publication date: August 27, 2009
    Applicant: DUAXES CORPORATION
    Inventor: Mitsugu Nagoya
  • Publication number: 20090178116
    Abstract: The present invention provides a technique for improving the security of access to contents. A virus/phishing site list contains a list of URLs of phishing sites, which masquerade as valid websites and are provided with an attempt to acquire private information including card numbers, PIN numbers and passwords, from users illegally. When a communication control unit receives, via a network, a packet that contains communication data for requesting access to a content, a search circuit compares the URL of the content to be accessed included in the communication data, with URLs of phishing sites included in the virus/phishing site list. If the address of the content to be accessed matches a URL of a phishing site, a process execution circuit will prohibit the access to the content.
    Type: Application
    Filed: August 25, 2005
    Publication date: July 9, 2009
    Applicant: Duaxes Corporation
    Inventors: Mitsugu Nagoya, Atsushi Suzuki
  • Publication number: 20090132509
    Abstract: The present invention provides a technique for enabling a high-speed communication control apparatus. A packet processing circuit of a communication control apparatus includes a user database, a virus list, a whitelist, a blacklist and a common category list. Upon acquisition of a request for access to a content, matching between information on a user who has sent the access request and the user database is performed by a search circuit, so as to authenticate the user. When the user is authenticated, the search circuit performs matching between the URL of the content to be accessed and the virus list, whitelist, blacklist and common category list. A process execution circuit controls the permission for the access based on the search result of the search circuit and determination conditions stored in a second database. The packet processing circuit is configured with a wired logic circuit.
    Type: Application
    Filed: March 28, 2005
    Publication date: May 21, 2009
    Applicant: DUAXES CORPORATION
    Inventor: Mitsugu Nagoya
  • Publication number: 20090132554
    Abstract: A data processing system includes a data processing unit which processes data acquired and a plurality of data retaining units which store databases used to process the data. Each of the plurality of data retaining units stores a primary database in common and stores the respective shares of a secondary database. The data processing system includes at least one more data retaining unit which can store the primary database and the respective shares of the secondary database.
    Type: Application
    Filed: May 20, 2005
    Publication date: May 21, 2009
    Applicant: DUAXES CORPORATION
    Inventor: Mitsugu Nagoya
  • Publication number: 20090100173
    Abstract: The present invention provides a technique for managing P2P communication appropriately. Each P2P node constituting a P2P network in a communication management system conducts P2P communication with another P2P node. A P2P node has a P2P connection to communicate with a P2P node. A node detector refers to communication data transmitted from or to a P2P node to detect identification information of a P2P node, and registers the information in a P2P node database. A communication control system possessed by an ISP refers to identification information stored in the P2P node database, so as to detect and perform filtering on P2P communication between P2P nodes.
    Type: Application
    Filed: May 25, 2006
    Publication date: April 16, 2009
    Applicant: DUAXES CORPORATION
    Inventors: Mitsugu Nagoya, Genta Iha
  • Patent number: 7484244
    Abstract: An object of the present invention is to provide an apparatus, a method, and a system for virus detection which can find even an unknown virus easily with no OS dependency. To achieve the foregoing object, the present invention provides a virus detection apparatus including an inspection computer to be connected to a mail server. The inspection computer includes file opening means for opening an attachment of e-mail transferred from said mail server, an I/O port for establishing interface connection with a PC, the PC being connected to the inspection computer to send and receive e-mail to/from the mail server through the inspection computer, virus inspecting means for detecting data of the attachment opened by said file opening means for access to said I/O port to inspect virus invasion, and warning means for outputting a warning signal from the virus inspecting means when access to the I/O port is detected.
    Type: Grant
    Filed: November 25, 2002
    Date of Patent: January 27, 2009
    Assignee: Duaxes Corporation
    Inventors: Mitsugu Nagoya, Mitsuji Matsumoto
  • Publication number: 20080281716
    Abstract: The present invention provides a technique for outputting an appropriate message in response to a request for access to a content or a service. A communication control apparatus receives a packet for requesting access to a content or a service and determines whether or not the access should be permitted. If the access is prohibited, the communication control apparatus will instruct a message output server to output a message such as an error message. A message retaining unit retains a message to be output to an access request source, with respect to each user of access request source, or each URL or each category of contents to be accessed. A registration acceptance unit accepts message registration and instructs a charging unit to charge a registration fee. The charging unit then performs processing for deducting the registration fee from the registrant's account.
    Type: Application
    Filed: January 31, 2006
    Publication date: November 13, 2008
    Applicant: Duaxes Corporation
    Inventors: Mitsugu Nagoya, Atsushi Suzuki
  • Publication number: 20080270360
    Abstract: A technology for achieving a high-speed data processing apparatus is provided. The communication control apparatus 10 includes a communication control section 2 on the receiving side, a packet processing circuit 20, and a communication control section 4 on the sending side. The communication control sections 2 and 4 have respective PHY processing sections 5a and 5b which process the physical layer of packets, and respective MAC processing sections 6a and 6b which process the MAC layer of the packets. The packet processing circuit 20 is composed of wired logic circuits, and performs filtering and other processing according to data included in the packets. The processing is executed by the dedicated hardware circuit without requiring a CPU or an OS.
    Type: Application
    Filed: July 7, 2005
    Publication date: October 30, 2008
    Inventor: Mitsugu Nagoya
  • Publication number: 20080196085
    Abstract: The present invention provides a technique for improving the security of access to contents. A virus/phishing site list contains a list of URLs of phishing sites, which masquerade as valid websites and are provided with an attempt to acquire private information including card numbers, PIN numbers and passwords, from users illegally. When a communication control unit receives, via a network, a packet that contains communication data for requesting access to a content, a search circuit compares the URL of the content to be accessed included in the communication data, with URLs of phishing sites included in the virus/phishing site list, regardless of the need for access control of the communication data. If the address of the content to be accessed matches a URL of a phishing site, a process execution circuit will prohibit the access to the content.
    Type: Application
    Filed: January 31, 2006
    Publication date: August 14, 2008
    Applicant: DUAXES CORPORATION
    Inventors: Mitsugu Nagoya, Atsushi Suzuki
  • Publication number: 20080062983
    Abstract: A method of duplicating protocol for making identical the order of reception and contents of packets on the two computers of a duplicated computer system with respect to packets of specific types of communication. On the first computer, each packet taken in is checked to determine whether the packet is a packet of the specific types of communication before protocol processing. If the packet is a packet of the specific types of communication, the packet is passed to the protocol processing process and added to a virtual queue created in its shared memory. On the second computer, each packet taken in is checked to determine whether the packet is a packet of the specific types of communication before protocol processing. If the packet is a packet of the specific types of communication, the packet is discarded, and the one at the head of the virtual queue in its shared memory is passed to the protocol processing process.
    Type: Application
    Filed: October 31, 2007
    Publication date: March 13, 2008
    Applicant: DUAXES CORPORATION
    Inventor: Mitsugu Nagoya
  • Patent number: 7340637
    Abstract: A method of duplicating servers and a duplicated server system that make seamless transition of service in case of server failures possible. The duplicated server system comprises first and second servers that are connected to a network and have the same network address, communication means for making high-speed communication between both servers possible, and switchover controller that designates the first server as the primary server put in operation for other computers and the second server as the secondary server in normal condition. When the first server receives a service request addressed to the system, it passes the service request to the application for processing. The first server sends the recovery data output by the application to the second server by means of the communication means.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: March 4, 2008
    Assignee: DUAXES Corporation
    Inventor: Mitsugu Nagoya
  • Patent number: 7328273
    Abstract: A method of duplicating protocol for making identical the order of reception and contents of packets on the two computers of a duplicated computer system with respect to packets of specific types of communication. On the first computer, each packet taken in is checked to determine whether the packet is a packet of the specific types of communication before protocol processing. If the packet is a packet of the specific types of communication, the packet is passed to the protocol processing process and added to a virtual queue created in its shared memory. On the second computer, if the packet is a packet of the specific types of communication, the packet is discarded, and the one at the head of the virtual queue in its shared memory is passed to the protocol processing process.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: February 5, 2008
    Assignee: DUAXES Corporation
    Inventor: Mitsugu Nagoya
  • Publication number: 20070136411
    Abstract: A CRC value calculator enables throughput to be improved while keeping down the increase in the size of the circuitry. This is achieved by using (n+1) basic CRC circuits to configure a CRC value calculator in which the width of the data processed during one clock cycle is m2n bits. For example, when m2n bits is the data width processed per calculator cycle, the CRC value calculator of this invention is configured by using selectors to serially connect a CRC circuit that processes every m2n bits, a CRC circuit that processes every m2(n?1) bits, . . . , and a CRC circuit that processes every m20 bits. This configuration makes it possible to calculate a correct CRC value even when the remainder of an input network frame is not a multiple of m2n bits. Selectors are used to select CRC circuit output according to process data width. Reduction of the operating frequency is avoided by using registers to form a pipeline between CRC circuits.
    Type: Application
    Filed: June 9, 2006
    Publication date: June 14, 2007
    Inventors: Toshihiro Katashita, Kenji Toda, Kazumi Sakamaki, Takeshi Inui, Tadamasa Takayama, Mitsugu Nagoya, Yasunori Terashima
  • Publication number: 20070067130
    Abstract: Network device testing equipment capable of testing network devices using small size packets and for a transferring ability and a filtering ability at a media speed is described. A configuration is adopted in which a Field Programmable Gate Array (FPGA) included in a transmitter or receiver on one or both of transmitting and receiving sides is connected directly to a physical layer chip of a network and computers on both the transmitting and receiving sides are connected thereto. Each of the FPGAs of the transmitter and receiver has a circuit which has an integrated function of transmitting a packet pattern generation function and a packet-receiving function, thereby enabling a test and an inspection in real time. When inspecting the filtering function, a hash table storing therein a hash value and a list of occurrence frequencies for hash values is utilized.
    Type: Application
    Filed: March 7, 2006
    Publication date: March 22, 2007
    Inventors: Kenji Toda, Toshihiro Katashita, Kazumi Sakamaki, Takeshi Inui, Mitsugu Nagoya, Yasunori Terashima
  • Patent number: 6701475
    Abstract: A boundary scan element includes a plurality of input terminal side boundary cells connected in series; a plurality of output terminal side boundary cells connected in series; a TAP circuit for controlling input/output of data to/from the boundary cells on the input/output terminal sides; a TDI terminal for receiving serial data to be supplied to the boundary cells; a TDO terminal for outputting the data from the boundary cells as serial data; a TCK terminal for receiving clock signals; and a TMS terminal for receiving a mode signal to switch an operation mode of the TAP circuit, wherein the boundary cells on the input/output terminal sides are connected in parallel between the TDI and TDO terminals, respectively, and wherein two sets of combinations composed of the input terminal side boundary cells, the output terminal boundary cells, the TDI terminal, the TDO terminal and the TAP circuit are provided.
    Type: Grant
    Filed: November 23, 1999
    Date of Patent: March 2, 2004
    Assignees: Koken Co. Ltd.
    Inventor: Mitsugu Nagoya
  • Publication number: 20040017828
    Abstract: A method of duplicating protocol for making identical the order of reception and contents of packets on the two computers of a duplicated computer system with respect to packets of specific types of communication. On the first computer, each packet taken in is checked to determine whether the packet is a packet of the specific types of communication before protocol processing. If the packet is a packet of the specific types of communication, the packet is passed to the protocol processing process and added to a virtual queue created in its shared memory. On the second computer, each packet taken in is checked to determine whether the packet is a packet of the specific types of communication before protocol processing. If the packet is a packet of the specific types of communication, the packet is discarded, and the one at the head of the virtual queue in its shared memory is passed to the protocol processing process.
    Type: Application
    Filed: May 14, 2003
    Publication date: January 29, 2004
    Inventor: Mitsugu Nagoya
  • Patent number: 6671840
    Abstract: A communication system includes boundary scan elements each having a plurality of boundary cells individually assigned to respective input terminals and output terminals, a TAP circuit for controlling input and output of data, a TDI terminal and TDO terminal for inputting or outputting serial data, a TCK terminal to which a clock signal is input, and a TMS terminal to which a mode signal for switching the operation mode is input; a plurality of terminal units connected with the respective boundary scan elements; and a communication controller connected in series with the boundary scan elements for individual control of the terminal units. Incoming communication lines between the boundary scan elements adjoining each other, and between the boundary scan elements and the communication controller, and an outgoing communication line between the communication controller and the boundary scan element positioned at the backmost are formed.
    Type: Grant
    Filed: November 23, 1999
    Date of Patent: December 30, 2003
    Assignees: Koken Co., Ltd.
    Inventor: Mitsugu Nagoya
  • Patent number: 6658614
    Abstract: There are provided a boundary scan element including a plurality of input-terminal-side boundary cells connected in series and assigned individually to respective input terminals, a plurality of output-terminal-side boundary cells connected in series and assigned individually to respective output terminals, a TAP circuit for controlling input and output of data to or from the input-terminal-side and output-terminal-side boundary cells, a TDI terminal for inputting serial data to be provided to the boundary cells, a TDO terminal for outputting data from the boundary cells as serial data, a TCK terminal to which a clock signal is input, and a TMS terminal to which a mode signal is input to switch an operation mode of the TAP circuit, characterized in that the input-terminal-side boundary cells and the output-terminal-side boundary cells are connected in parallel between the TDI terminal and the TDO terminal; and a communication system using the same.
    Type: Grant
    Filed: November 23, 1999
    Date of Patent: December 2, 2003
    Assignees: Koken Co., Ltd.
    Inventor: Mitsugu Nagoya
  • Patent number: 6622262
    Abstract: A fault tolerant computer system is provided which can immediately detect that its main computer is down and which can accurately pinpoint the point where the processing is suspended, without delaying the processing which the computer should originally execute. The fault tolerant computer system has: the main computer; an auxiliary computer for normally virtually executing the same processing as that executed by the main computer; a communication element connected to an object, the communication element being a boundary scan element; and a switch unit for switching connection between the communication element and either the main computer or the auxiliary computer. The switch unit switches the connection in accordance with the presence or absence of a clock signal supplied from the main computer to the communication element.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: September 16, 2003
    Assignee: Koken Co., Ltd.
    Inventor: Mitsugu Nagoya