Patents by Inventor Mitsuhiko Sakai
Mitsuhiko Sakai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12057416Abstract: A semiconductor device includes: a semiconductor substrate having a first main surface; an aluminum electrode having a first surface facing the first main surface and a second surface opposite to the first surface, the aluminum electrode being disposed on the semiconductor substrate; a passivation film that covers a peripheral edge of the second surface and that is provided with an opening from which a portion of the second surface is exposed; a copper film disposed on the second surface exposed from the opening so as to be separated from the passivation film; and a metal film disposed on the second surface exposed from between the passivation film and the copper film. The metal film is constituted of at least one selected from a group consisting of a nickel film, a tantalum film, a tantalum nitride film, a tungsten film, a titanium film, and a titanium nitride film.Type: GrantFiled: March 11, 2020Date of Patent: August 6, 2024Assignee: Sumitomo Electric Industries, Ltd.Inventor: Mitsuhiko Sakai
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Patent number: 11916029Abstract: A semiconductor device of the present disclosure includes: a semiconductor substrate having a first main surface; a first aluminum electrode having a first surface facing the first main surface and a second surface opposite to the first surface, the first aluminum electrode being disposed on the semiconductor substrate; a passivation film that covers a peripheral edge of the second surface and that is provided with an opening from which a portion of the second surface is exposed; and a copper film. The second surface exposed from the opening is provided with a recess that is depressed toward the first surface. The copper film is disposed in the recess.Type: GrantFiled: March 10, 2020Date of Patent: February 27, 2024Assignee: Sumitomo Electric Industries, Ltd.Inventors: Mitsuhiko Sakai, Hirotaka Oomori
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Publication number: 20230197906Abstract: A semiconductor light emitting device includes a conductive substrate and a first metal layer disposed on the substrate. The first metal layer is formed so as to be electrically connected with the substrate, and the first metal layer includes an Au based material. A joining layer is formed on the first metal layer. The joining layer includes a second metal layer including Au and a third metal layer including Au. A metallic contact layer and an insulating layer are formed on the joining layer. A semiconductor layer is formed on the metallic contact layer and the insulating layer and includes a red-based light emitting layer. An electrode is formed on the semiconductor layer and is made of metal. The insulating layer includes a patterned aperture, and at least a part of the metallic contact layer is formed in the aperture.Type: ApplicationFiled: February 15, 2023Publication date: June 22, 2023Applicant: ROHM CO., LTD.Inventors: Masakazu TAKAO, Mitsuhiko SAKAI, Kazuhiko SENDA
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Patent number: 11616172Abstract: A semiconductor light emitting device includes a conductive substrate and a first metal layer disposed on the substrate. The first metal layer is formed so as to be electrically connected with the substrate, and the first metal layer includes an Au based material. A joining layer is formed on the first metal layer. The joining layer includes a second metal layer including Au and a third metal layer including Au. A metallic contact layer and an insulating layer are formed on the joining layer. A semiconductor layer is formed on the metallic contact layer and the insulating layer and includes a red-based light emitting layer. An electrode is formed on the semiconductor layer and is made of metal. The insulating layer includes a patterned aperture, and at least a part of the metallic contact layer is formed in the aperture.Type: GrantFiled: October 18, 2019Date of Patent: March 28, 2023Assignee: ROHM CO., LTD.Inventors: Masakazu Takao, Mitsuhiko Sakai, Kazuhiko Senda
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Publication number: 20220181281Abstract: A semiconductor device of the present disclosure includes: a semiconductor substrate having a first main surface; a first aluminum electrode having a first surface facing the first main surface and a second surface opposite to the first surface, the first aluminum electrode being disposed on the semiconductor substrate; a passivation film that covers a peripheral edge of the second surface and that is provided with an opening from which a portion of the second surface is exposed; and a copper film. The second surface exposed from the opening is provided with a recess that is depressed toward the first surface. The copper film is disposed in the recess.Type: ApplicationFiled: March 10, 2020Publication date: June 9, 2022Inventors: Mitsuhiko SAKAI, Hirotaka OOMORI
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Publication number: 20220181279Abstract: A semiconductor device includes: a semiconductor substrate having a first main surface; an aluminum electrode having a first surface facing the first main surface and a second surface opposite to the first surface, the aluminum electrode being disposed on the semiconductor substrate; a passivation film that covers a peripheral edge of the second surface and that is provided with an opening from which a portion of the second surface is exposed; a copper film disposed on the second surface exposed from the opening so as to be separated from the passivation film; and a metal film disposed on the second surface exposed from between the passivation film and the copper film. The metal film is constituted of at least one selected from a group consisting of a nickel film, a tantalum film, a tantalum nitride film, a tungsten film, a titanium film, and a titanium nitride film.Type: ApplicationFiled: March 11, 2020Publication date: June 9, 2022Inventor: Mitsuhiko SAKAI
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Publication number: 20220123141Abstract: A silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. The first main surface is provided with a gate trench having a side surface and a bottom surface contiguous to the side surface. The gate insulating film is in contact with each of the side surface and the bottom surface. The gate electrode is provided on the gate insulating film. The separation insulating film is provided on the gate electrode. The first electrode is provided on the separation insulating film. The second electrode is provided on the second main surface. The separation insulating film electrically separates the gate electrode and the first electrode from each other. Each of the gate insulating film, the gate electrode, and the separation insulating film, and a portion of the first electrode are provided in the gate trench.Type: ApplicationFiled: January 29, 2020Publication date: April 21, 2022Inventors: Mitsuhiko SAKAI, Toru HIYOSHI
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Patent number: 10608107Abstract: A silicon carbide substrate includes a first impurity region, a second impurity region in contact with the first impurity region and having p type, a third impurity region on the first impurity region and the second impurity region and having n type, a body region, and a source region. A gate insulating film is in contact with the source region, the body region and the third impurity region at a side surface, and in contact with the third impurity region at a bottom surface. When viewed in a direction perpendicular to a main surface, the second impurity region contains the bottom surface, and an area of the second impurity region is greater than an area of the bottom surface, and is not more than three times the area of the bottom surface. An impurity concentration of the second impurity region exceeds 1×1019 cm?3, and is not more than 1×1021 cm?3.Type: GrantFiled: February 27, 2017Date of Patent: March 31, 2020Assignee: Sumitomo Electric Industries, Ltd.Inventors: Mitsuhiko Sakai, Toru Hiyoshi, So Tanaka
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Publication number: 20200052163Abstract: A semiconductor light emitting device includes a conductive substrate and a first metal layer disposed on the substrate. The first metal layer is formed so as to be electrically connected with the substrate, and the first metal layer includes an Au based material. A joining layer is formed on the first metal layer. The joining layer includes a second metal layer including Au and a third metal layer including Au. A metallic contact layer and an insulating layer are formed on the joining layer. A semiconductor layer is formed on the metallic contact layer and the insulating layer and includes a red-based light emitting layer. An electrode is formed on the semiconductor layer and is made of metal. The insulating layer includes a patterned aperture, and at least a part of the metallic contact layer is formed in the aperture.Type: ApplicationFiled: October 18, 2019Publication date: February 13, 2020Applicant: ROHM CO., LTD.Inventors: Masakazu TAKAO, Mitsuhiko SAKAI, Kazuhiko SENDA
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Patent number: 10483435Abstract: A semiconductor light emitting device includes a conductive substrate and a first metal layer disposed on the substrate. The first metal layer is formed so as to be electrically connected with the substrate, and the first metal layer includes an Au based material. A joining layer is formed on the first metal layer. The joining layer includes a second metal layer including Au and a third metal layer including Au. A metallic contact layer and an insulating layer are formed on the joining layer. A semiconductor layer is formed on the metallic contact layer and the insulating layer and includes a red-based light emitting layer. An electrode is formed on the semiconductor layer and is made of metal. The insulating layer includes a patterned aperture, and at least a part of the metallic contact layer is formed in the aperture.Type: GrantFiled: June 22, 2018Date of Patent: November 19, 2019Assignee: ROHM CO., LTD.Inventors: Masakazu Takao, Mitsuhiko Sakai, Kazuhiko Senda
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Publication number: 20190198622Abstract: A first main surface is provided with: a gate trench defined by a first side surface and a first bottom surface; and a source trench defined by a second side surface and a second bottom surface. A silicon carbide substrate includes a drift region, a body region, a source region, a first region, and a second region. The first region is in contact with the second region. A gate insulating film is in contact with the drift region, the body region, and the source region at the first side surface, and is in contact with the drift region at the first bottom surface. A source electrode is in contact with the second region at the second side surface and the second bottom surface.Type: ApplicationFiled: June 20, 2017Publication date: June 27, 2019Inventors: Kosuke UCHIDA, Toru HIYOSHI, Mitsuhiko SAKAI
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Publication number: 20190172943Abstract: A silicon carbide substrate includes a first impurity region, a second impurity region in contact with the first impurity region and having p type, a third impurity region on the first impurity region and the second impurity region and having n type, a body region, and a source region. A gate insulating film is in contact with the source region, the body region and the third impurity region at a side surface, and in contact with the third impurity region at a bottom surface. When viewed in a direction perpendicular to a main surface, the second impurity region contains the bottom surface, and an area of the second impurity region is greater than an area of the bottom surface, and is not more than three times the area of the bottom surface. An impurity concentration of the second impurity region exceeds 1×1019 cm?3, and is not more than 1×1021 cm?3.Type: ApplicationFiled: February 27, 2017Publication date: June 6, 2019Inventors: Mitsuhiko Sakai, Toru Hiyoshi, So Tanaka
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Publication number: 20190140056Abstract: A silicon carbide layer includes a drift region, a body region and a source region. The drift region constitutes a first main surface and has a first conductivity type. The body region is provided on the drift region, and has a second conductivity type. It is provided on the body region to be separated from the drift region, constitutes a second main surface, and has the first conductivity type. The silicon carbide layer is provided with a trench including a first side wall portion and a first bottom portion. The silicon carbide layer is embedded in the drift region to face the first bottom portion, and includes a second conductivity type region having the second conductivity type. The second conductivity type region is electrically connected to the source region.Type: ApplicationFiled: December 17, 2018Publication date: May 9, 2019Inventors: Keiji Wada, Takeyoshi Masuda, Hideto Tamaso, Yu Saitoh, Toru Hiyoshi, Mitsuhiko Sakai
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Patent number: 10192960Abstract: A silicon carbide layer includes a drift region, a body region and a source region. The drift region constitutes a first main surface and has a first conductivity type. The body region is provided on the drift region, and has a second conductivity type. It is provided on the body region to be separated from the drift region, constitutes a second main surface, and has the first conductivity type. The silicon carbide layer is provided with a trench including a first side wall portion and a first bottom portion. The silicon carbide layer is embedded in the drift region to face the first bottom portion, and includes a second conductivity type region having the second conductivity type. The second conductivity type region is electrically connected to the source region.Type: GrantFiled: June 10, 2014Date of Patent: January 29, 2019Assignee: Sumitomo Electric Industries, Ltd.Inventors: Keiji Wada, Takeyoshi Masuda, Hideto Tamaso, Yu Saitoh, Toru Hiyoshi, Mitsuhiko Sakai
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Publication number: 20180301599Abstract: A semiconductor light emitting device includes a conductive substrate and a first metal layer disposed on the substrate. The first metal layer is formed so as to be electrically connected with the substrate, and the first metal layer includes an Au based material. A joining layer is formed on the first metal layer. The joining layer includes a second metal layer including Au and a third metal layer including Au. A metallic contact layer and an insulating layer are formed on the joining layer. A semiconductor layer is formed on the metallic contact layer and the insulating layer and includes a red-based light emitting layer. An electrode is formed on the semiconductor layer and is made of metal. The insulating layer includes a patterned aperture, and at least a part of the metallic contact layer is formed in the aperture.Type: ApplicationFiled: June 22, 2018Publication date: October 18, 2018Applicant: ROHM CO., LTD.Inventors: Masakazu TAKAO, Mitsuhiko SAKAI, Kazuhiko SENDA
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Patent number: 10056247Abstract: In accordance with the following step of a method of manufacturing a MOSFET, a first cutting step of cutting a silicon carbide wafer along a plane substantially parallel to a {11-20} plane is performed. After the first cutting step, a second cutting step of cutting the silicon carbide wafer along a plane substantially perpendicular to the {11-20} plane and substantially perpendicular to the first main surface is performed.Type: GrantFiled: October 7, 2015Date of Patent: August 21, 2018Assignee: Sumitomo Electric Industries, Ltd.Inventors: Mitsuhiko Sakai, Hiroyuki Kitabayashi
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Patent number: 10032961Abstract: A semiconductor light emitting device includes a conductive substrate and a first metal layer disposed on the substrate. The first metal layer is formed so as to be electrically connected with the substrate, and the first metal layer includes an Au based material. A joining layer is formed on the first metal layer. The joining layer includes a second metal layer including Au and a third metal layer including Au. A metallic contact layer and an insulating layer are formed on the joining layer. A semiconductor layer is formed on the metallic contact layer and the insulating layer and includes a red-based light emitting layer. An electrode is formed on the semiconductor layer and is made of metal. The insulating layer includes a patterned aperture, and at least a part of the metallic contact layer is formed in the aperture.Type: GrantFiled: September 26, 2017Date of Patent: July 24, 2018Assignee: ROHM CO., LTD.Inventors: Masakazu Takao, Mitsuhiko Sakai, Kazuhiko Senda
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Publication number: 20180019381Abstract: A semiconductor light emitting device includes a conductive substrate and a first metal layer disposed on the substrate. The first metal layer is formed so as to be electrically connected with the substrate, and the first metal layer includes an Au based material. A joining layer is formed on the first metal layer. The joining layer includes a second metal layer including Au and a third metal layer including Au. A metallic contact layer and an insulating layer are formed on the joining layer. A semiconductor layer is formed on the metallic contact layer and the insulating layer and includes a red-based light emitting layer. An electrode is formed on the semiconductor layer and is made of metal. The insulating layer includes a patterned aperture, and at least a part of the metallic contact layer is formed in the aperture.Type: ApplicationFiled: September 26, 2017Publication date: January 18, 2018Applicant: ROHM CO., LTD.Inventors: Masakazu TAKAO, Mitsuhiko SAKAI, Kazuhiko SENDA
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Patent number: 9831126Abstract: A method of manufacturing a semiconductor device includes the steps of preparing a semiconductor substrate including a semiconductor layer having a first main surface and a second main surface located opposite to the first main surface and an epitaxial layer formed on the first main surface, forming a trench having a sidewall passing through the epitaxial layer and reaching the semiconductor layer and a bottom portion continuing to the sidewall and located in the semiconductor layer, decreasing a thickness of the semiconductor layer by grinding the second main surface, forming an electrode layer on the ground second main surface, achieving ohmic contact between the second main surface and the electrode layer by laser annealing, and obtaining individual substrates by forming a cutting portion along the trench and dividing the semiconductor substrate along the cutting portion.Type: GrantFiled: April 29, 2015Date of Patent: November 28, 2017Assignee: Sumitomo Electric Industries, Ltd.Inventor: Mitsuhiko Sakai
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Publication number: 20170338100Abstract: In accordance with the following step of a method of manufacturing a MOSFET, a first cutting step of cutting a silicon carbide wafer along a plane substantially parallel to a {11-20} plane is performed. After the first cutting step, a second cutting step of cutting the silicon carbide wafer along a plane substantially perpendicular to the {11-20} plane and substantially perpendicular to the first main surface is performed.Type: ApplicationFiled: October 7, 2015Publication date: November 23, 2017Inventors: Mitsuhiko Sakai, Hiroyuki Kitabayashi