Patents by Inventor Mitsuhiko Sakai

Mitsuhiko Sakai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9786819
    Abstract: A semiconductor light emitting device includes a conductive substrate and a first metal layer disposed on the substrate. The first metal layer is formed so as to be electrically connected with the substrate, and the first metal layer includes an Au based material. A joining layer is formed on the first metal layer. The joining layer includes a second metal layer including Au and a third metal layer including Au. A metallic contact layer and an insulating layer are formed on the joining layer. A semiconductor layer is formed on the metallic contact layer and the insulating layer and includes a red-based light emitting layer. An electrode is formed on the semiconductor layer and is made of metal. The insulating layer includes a patterned aperture, and at least a part of the metallic contact layer is formed in the aperture.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: October 10, 2017
    Assignee: ROHM CO., LTD.
    Inventors: Masakazu Takao, Mitsuhiko Sakai, Kazuhiko Senda
  • Publication number: 20170154818
    Abstract: A method of manufacturing a semiconductor device includes the steps of preparing a semiconductor substrate including a semiconductor layer having a first main surface and a second main surface located opposite to the first main surface and epitaxial layer formed on the first main surface, forming a trench having a sidewall passing through the epitaxial layer and reaching the semiconductor layer and a bottom portion continuing to the sidewall and located in the semiconductor layer, decreasing a thickness of the semiconductor layer by grinding the second main surface, forming an electrode layer on the ground second main surface, achieving ohmic contact between the second main surface and the electrode layer by laser annealing, and obtaining individual substrates by forming a cubing portion along the trench and dividing the semiconductor substrate along the cutting portion.
    Type: Application
    Filed: April 29, 2015
    Publication date: June 1, 2017
    Inventor: Mitsuhiko SAKAI
  • Patent number: 9647081
    Abstract: A method for manufacturing a silicon carbide semiconductor device includes steps of preparing a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, forming a groove portion in the first main surface of the silicon carbide substrate, and cutting the silicon carbide substrate at the groove portion. The step of forming the groove portion includes a step of thermally etching the silicon carbide substrate using chlorine. Thereby, a method for manufacturing a silicon carbide semiconductor device capable of suppressing damage to a chip is provided.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: May 9, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Wada, Takeyoshi Masuda, Mitsuhiko Sakai
  • Patent number: 9640619
    Abstract: A method of manufacturing a wide band gap semiconductor device includes the steps of preparing a wide band gap semiconductor substrate, separating the wide band gap semiconductor substrate into a plurality of first semiconductor chips, fixing the plurality of first semiconductor chips on a fixation member, measuring a breakdown voltage of each of the first semiconductor chips while immersing at least the first semiconductor chips in inert liquid, and after the step of measuring a breakdown voltage of each of the first semiconductor chips, providing a plurality of second semiconductor chips each having each of the first semiconductor chips fixed on the fixation member, by cutting the fixation member.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: May 2, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Mitsuhiko Sakai
  • Patent number: 9607905
    Abstract: A method of measuring a breakdown voltage of a semiconductor element includes the steps below. A wafer provided with a plurality of semiconductor elements each having an electrode is prepared. The wafer is divided into a plurality of chips provided with at least one semiconductor element. After the step of division into the plurality of chips, a breakdown voltage of the semiconductor element is measured while a probe is in contact with the electrode of the semiconductor element in an insulating liquid.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: March 28, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Mitsuhiko Sakai, Susumu Yoshimoto
  • Publication number: 20160365489
    Abstract: A semiconductor light emitting device includes a conductive substrate and a first metal layer disposed on the substrate. The first metal layer is formed so as to be electrically connected with the substrate, and the first metal layer includes an Au based material. A joining layer is formed on the first metal layer. The joining layer includes a second metal layer including Au and a third metal layer including Au. A metallic contact layer and an insulating layer are formed on the joining layer. A semiconductor layer is formed on the metallic contact layer and the insulating layer and includes a red-based light emitting layer. An electrode is formed on the semiconductor layer and is made of metal. The insulating layer includes a patterned aperture, and at least a part of the metallic contact layer is formed in the aperture.
    Type: Application
    Filed: August 26, 2016
    Publication date: December 15, 2016
    Applicant: ROHM CO., LTD.
    Inventors: Masakazu TAKAO, Mitsuhiko SAKAI, Kazuhiko SENDA
  • Patent number: 9450145
    Abstract: A high luminance semiconductor light emitting device including a metallic reflecting layer formed using a non-transparent semiconductor substrate is provided. The device includes a GaAs substrate; a metal layer disposed on the GaAs substrate; and a light emitting diode structure. The light emitting diode structure includes a patterned metal contact layer and a patterned insulating layer disposed on the metal layer, a p type cladding layer disposed on the patterned metal contact layer and the patterned insulating layer, a multi-quantum well layer disposed on the p type cladding layer, an n type cladding layer disposed on the multi-quantum well layer, and a window layer disposed on the n type cladding layer. The GaAs substrate and the light emitting diode structure are bonded by using the metal layer.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: September 20, 2016
    Assignee: ROHM CO., LTD.
    Inventors: Masakazu Takao, Mitsuhiko Sakai, Kazuhiko Senda
  • Patent number: 9397155
    Abstract: A silicon carbide semiconductor device includes a silicon carbide layer, an element region including a semiconductor element portion formed in the silicon carbide layer, a JTE region (first electric field relaxing region), an insulating film disposed on a first main surface and covering the JTE region, and a pad electrode electrically connected to the JTE region. The pad electrode includes an extension portion extending from an end of the JTE region close to the element region in a peripheral direction from the element region toward the JTE region, the extension portion being disposed on the insulating film. The extension portion overlies at least a portion of the JTE region.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: July 19, 2016
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Wada, Toru Hiyoshi, Masaki Furumai, Mitsuhiko Sakai, Kosuke Uchida
  • Publication number: 20160204086
    Abstract: A method of manufacturing a wide band gap semiconductor device includes the steps of preparing a wide band gap semiconductor substrate, separating the wide band gap semiconductor substrate into a plurality of first semiconductor chips (80), fixing the plurality of first semiconductor chips (80) on a fixation member (70), measuring a breakdown voltage of each of the first semiconductor chips (80) while immersing at least the first semiconductor chips (80) in inert liquid (91), and after the step of measuring a breakdown voltage of each of the first semiconductor chips (80), providing a plurality of second semiconductor chips each having each of the first semiconductor chips (80) fixed on the fixation member (70), by cutting the fixation member (70).
    Type: Application
    Filed: July 17, 2014
    Publication date: July 14, 2016
    Inventor: Mitsuhiko Sakai
  • Publication number: 20160204220
    Abstract: A method for manufacturing a silicon carbide semiconductor device includes steps of preparing a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, forming a groove portion in the first main surface of the silicon carbide substrate, and cutting the silicon carbide substrate at the groove portion. The step of forming the groove portion includes a step of thermally etching the silicon carbide substrate using chlorine. Thereby, a method for manufacturing a silicon carbide semiconductor device capable of suppressing damage to a chip is provided.
    Type: Application
    Filed: July 9, 2014
    Publication date: July 14, 2016
    Inventors: Keiji Wada, Takeyoshi Masuda, Mitsuhiko Sakai
  • Publication number: 20160197149
    Abstract: A first electrode being in contact with the first main surface of the silicon carbide semiconductor substrate and in ohmic junction with the silicon carbide semiconductor substrate is formed. At least a portion of the silicon carbide semiconductor substrate on a side of the second main surface is removed. A second electrode in contact with the second main surface of the silicon carbide semiconductor substrate exposed by removing at least a portion of the silicon carbide semiconductor substrate and in ohmic junction with the silicon carbide semiconductor substrate is formed. A metal layer being in electrical contact with a fourth main surface of the second electrode is formed. A thickness of the metal layer is greater than a thickness of the silicon carbide semiconductor substrate after the removal of at least a portion of the silicon carbide semiconductor substrate.
    Type: Application
    Filed: July 4, 2014
    Publication date: July 7, 2016
    Inventor: Mitsuhiko SAKAI
  • Publication number: 20160181372
    Abstract: A silicon carbide layer includes a drift region, a body region and a source region. The drift region constitutes a first main surface and has a first conductivity type. The body region is provided on the drift region, and has a second conductivity type. It is provided on the body region to be separated from the drift region, constitutes a second main surface, and has the first conductivity type. The silicon carbide layer is provided with a trench including a first side wall portion and a first bottom portion. The silicon carbide layer is embedded in the drift region to face the first bottom portion, and includes a second conductivity type region having the second conductivity type. The second conductivity type region is electrically connected to the source region.
    Type: Application
    Filed: June 10, 2014
    Publication date: June 23, 2016
    Inventors: Keiji Wada, Takeyoshi Masuda, Hideto Tamaso, Yu Saitoh, Toru Hiyoshi, Mitsuhiko Sakai
  • Publication number: 20160163800
    Abstract: A semiconductor layer having an upper surface and an end surface intersecting with the upper surface, an upper electrode (source electrode) formed on the upper surface and electrically connected to the semiconductor layer, and a protecting film extending from over at least a portion of the upper surface to over at least a portion of the end surface are provided.
    Type: Application
    Filed: May 28, 2014
    Publication date: June 9, 2016
    Inventor: Mitsuhiko Sakai
  • Publication number: 20160079349
    Abstract: A silicon carbide semiconductor device includes a silicon carbide layer, an element region including a semiconductor element portion formed in the silicon carbide layer, a JTE region (first electric field relaxing region), an insulating film disposed on a first main surface and covering the JTE region, and a pad electrode electrically connected to the JTE region. The pad electrode includes an extension portion extending from an end of the JTE region close to the element region in a peripheral direction from the element region toward the JTE region, the extension portion being disposed on the insulating film. The extension portion overlies at least a portion of the JTE region.
    Type: Application
    Filed: November 19, 2015
    Publication date: March 17, 2016
    Inventors: Keiji Wada, Toru Hiyoshi, Masaki Furumai, Mitsuhiko Sakai, Kosuke Uchida
  • Publication number: 20160064292
    Abstract: A method of measuring a breakdown voltage of a semiconductor element includes the steps below. A wafer provided with a plurality of semiconductor elements each having an electrode is prepared. The wafer is divided into a plurality of chips provided with at least one semiconductor element. After the step of division into the plurality of chips, a breakdown voltage of the semiconductor element is measured while a probe is in contact with the electrode of the semiconductor element in an insulating liquid.
    Type: Application
    Filed: September 2, 2015
    Publication date: March 3, 2016
    Inventors: Mitsuhiko Sakai, Susumu Yoshimoto
  • Publication number: 20160056332
    Abstract: A high luminance semiconductor light emitting device including a metallic reflecting layer formed using a non-transparent semiconductor substrate is provided. The device includes a GaAs substrate; a metal layer disposed on the GaAs substrate; and a light emitting diode structure. The light emitting diode structure includes a patterned metal contact layer and a patterned insulating layer disposed on the metal layer, a p type cladding layer disposed on the patterned metal contact layer and the patterned insulating layer, a multi-quantum well layer disposed on the p type cladding layer, an n type cladding layer disposed on the multi-quantum well layer, and a window layer disposed on the n type cladding layer. The GaAs substrate and the light emitting diode structure are bonded by using the metal layer.
    Type: Application
    Filed: October 30, 2015
    Publication date: February 25, 2016
    Applicant: ROHM CO., LTD.
    Inventors: Masakazu TAKAO, Mitsuhiko SAKAI, Kazuhiko SENDA
  • Patent number: 9224816
    Abstract: A silicon carbide semiconductor device includes a silicon carbide layer, an element region including a semiconductor element portion formed in the silicon carbide layer, a JTE region (first electric field relaxing region), an insulating film disposed on a first main surface and covering the JTE region, and a pad electrode electrically connected to the JTE region. The pad electrode includes an extension portion extending from an end of the JTE region close to the element region in a peripheral direction from the element region toward the JTE region, the extension portion being disposed on the insulating film. The extension portion overlies at least a portion of the JTE region.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: December 29, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Wada, Toru Hiyoshi, Masaki Furumai, Mitsuhiko Sakai, Kosuke Uchida
  • Publication number: 20150371901
    Abstract: A method of manufacturing a semiconductor device includes a step of preparing a semiconductor substrate including a semiconductor layer and an epitaxial layer formed on the semiconductor layer, a first division step of obtaining first individual pieces by dividing the semiconductor substrate so as to pass through a central region including a central point of the semiconductor substrate and having a diameter of 10 mm, and a second division step of obtaining second individual pieces by subdividing the first individual piece.
    Type: Application
    Filed: April 29, 2015
    Publication date: December 24, 2015
    Inventor: Mitsuhiko SAKAI
  • Publication number: 20150371902
    Abstract: A method of manufacturing a semiconductor device includes the steps of preparing a semiconductor substrate including a semiconductor layer having a first main surface and a second main surface located opposite to the first main surface and epitaxial layer formed on the first main surface, forming a trench having a sidewall passing through the epitaxial layer and reaching the semiconductor layer and a bottom portion continuing to the sidewall and located in the semiconductor layer, decreasing a thickness of the semiconductor layer by grinding the second main surface, forming an electrode layer on the ground second main surface, achieving ohmic contact between the second main surface and the electrode layer by laser annealing, and obtaining individual substrates by forming a cubing portion along the trench and dividing the semiconductor substrate along the cutting portion.
    Type: Application
    Filed: April 29, 2015
    Publication date: December 24, 2015
    Inventor: Mitsuhiko SAKAI
  • Publication number: 20150348774
    Abstract: A breakdown voltage measuring method includes the steps of measuring a breakdown voltage of a semiconductor element in a state where a surface of the semiconductor element formed in a semiconductor substrate is covered with a high boiling point fluorine fluid having a boiling point of 90° C. or higher, and cleaning the semiconductor substrate, including the semiconductor element for which the breakdown voltage is measured, with a low boiling point fluorine inert fluid having a boiling point of 80° C. or lower. Accordingly, a breakdown voltage measuring method capable of suppressing generation of an electric discharge during the measurement of the breakdown voltage and suppressing a residue of a foreign object on the cleaned semiconductor substrate, and a semiconductor device to which the breakdown voltage measuring method is implemented are provided.
    Type: Application
    Filed: April 29, 2015
    Publication date: December 3, 2015
    Inventor: Mitsuhiko SAKAI