Patents by Inventor Mitsuhiro Abe
Mitsuhiro Abe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240066504Abstract: Provided is a technique for molding a functional material without deteriorating the function of the functional material. A method for producing a functional material molded article of the present disclosure includes: dispersing a functional material in a water-alcohol mixed solution to obtain a liquid dispersion; impregnating a porous molding base material with the liquid dispersion to obtain an impregnated product; and drying the impregnated product.Type: ApplicationFiled: February 1, 2022Publication date: February 29, 2024Applicant: JAPAN AEROSPACE EXPLORATION AGENCYInventors: Asuka SHIMA, Yoshitsugu SONE, Motohiko SATO, Takayuki ABE, Mitsuhiro INOUE
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Patent number: 11915778Abstract: A semiconductor memory device includes: a core unit including first and second memory cell groups; and a control circuit. The control circuit is configured to, in response to a read command including designation of a first address and designation of a second address, read first data from the first memory cell group, read second data from the second memory cell group, and output third data and fourth data in parallel. The first and second addresses correspond to the first and second memory cell groups, respectively. The designation of the second address is made after the designation of the first address. The third data corresponds to the read first data. The fourth data corresponds to the read second data.Type: GrantFiled: March 15, 2022Date of Patent: February 27, 2024Assignee: Kioxia CorporationInventors: Daisuke Arizono, Akio Sugahara, Mitsuhiro Abe, Mitsuaki Honma
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Publication number: 20230317179Abstract: A semiconductor memory device includes a first pad, a clock generation circuit configured to generate a first clock, an output circuit configured to output the first clock through the first pad, a designation circuit configured to designate one of a plurality of contiguous times slots, each of which is set with respect to clock cycles of the first clock, and a peak control circuit configured to execute an operation that generates a current peak, at a timing corresponding to the designated time slot.Type: ApplicationFiled: August 30, 2022Publication date: October 5, 2023Inventors: Mitsuhiro ABE, Yasuhiro HIRASHIMA, Mitsuaki HONMA
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Publication number: 20230298641Abstract: A semiconductor memory device includes a memory cell array, a storing unit that stores data read out from the memory cell array in storage circuits, an output circuit, and a control circuit. In response to a read request, the control circuit adjusts the value of a read pointer of the storing unit, controls the storing unit to sequentially output to the output circuit first and second data stored in first and second storage circuits of the storing unit, respectively, the read pointer having a first value that references the first storage circuit when the first data is output, and a second value that references the second storage circuit when the second data is output, and controls the output circuit to transmit the first and second data to the memory controller as dummy data, and thereafter to transmit at least third data to the memory controller as read data.Type: ApplicationFiled: August 26, 2022Publication date: September 21, 2023Inventors: Shintaro HAYASHI, Mitsuhiro ABE, Naoaki KANAGAWA
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Publication number: 20230282257Abstract: A memory system includes a memory controller and a semiconductor storage device including a power supply pad, first, second, third, and fourth signal pads to which first, second, third, and fourth signals are respectively input, a memory cell array, a data register, and a control circuit executing an operation to output data stored in the data register through the fourth signal pad. The memory controller performs a mode setting operation by toggling the third signal input, after at least the first or second signal has been switched at a first timing after supplying power to the power supply pad, perform an initial setting operation by transmitting a power-on read command at a second timing after the first timing, and transmit a data-out command, at a third timing after the second timing. The semiconductor storage device receives the power-on read and data-out commands via the first and second signal pads.Type: ApplicationFiled: August 30, 2022Publication date: September 7, 2023Inventors: Takehisa KUROSAWA, Akio SUGAHARA, Mitsuhiro ABE, Hisashi FUJIKAWA, Yuji NAGAI, Zhao LU
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Publication number: 20230105932Abstract: A surface coated cutting tool includes a tool substrate; and a hard coating layer on the tool substrate. The hard coating layer includes, in sequence from the tool substrate toward a surface of the tool, a titanium carbonitride inner layer, a titanium nitride lower intermediate layer, a titanium carbonitride upper intermediate layer, a titanium oxycarbonitride bonding auxiliary layer, and an aluminum oxide outer layer. Titanium nitride grain boundaries in the lower intermediate layer and titanium carbonitride grain boundaries in the upper intermediate layer are continuous from titanium carbonitride grain boundaries in the inner layer. The texture coefficient TC(422) of titanium carbonitride in the inner layer and the upper intermediate layer is 3.0 or more, and the texture coefficient TC(0 0 12) of ?-aluminum oxide in the outer layer is 5.0 or more.Type: ApplicationFiled: June 5, 2020Publication date: April 6, 2023Applicant: MITSUBISHI MATERIALS CORPORATIONInventors: Eiji Nakamura, Mitsuhiro Abe, Kazuhiro Kawano
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Publication number: 20230109388Abstract: A semiconductor memory device includes: a core unit including first and second memory cell groups; and a control circuit. The control circuit is configured to, in response to a read command including designation of a first address and designation of a second address, read first data from the first memory cell group, read second data from the second memory cell group, and output third data and fourth data in parallel. The first and second addresses correspond to the first and second memory cell groups, respectively. The designation of the second address is made after the designation of the first address. The third data corresponds to the read first data. The fourth data corresponds to the read second data.Type: ApplicationFiled: March 15, 2022Publication date: April 6, 2023Applicant: Kioxia CorporationInventors: Daisuke ARIZONO, Akio SUGAHARA, Mitsuhiro ABE, Mitsuaki HONMA
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Publication number: 20220230665Abstract: According to one embodiment, a semiconductor memory device includes: a first delay circuit configured to delay a first signal and provide a variable delay time; a first select circuit configured to select a second signal or a third signal based on the first signal delayed by the first delay circuit; a first output buffer configured to output a fourth signal based on a signal selected by the first select circuit; a first output pad configured to externally output the fourth signal; and a counter configured to count a number of times the fourth signal is output.Type: ApplicationFiled: April 8, 2022Publication date: July 21, 2022Applicant: Kioxia CorporationInventors: Yasuhiro HIRASHIMA, Mitsuhiro ABE, Norichika ASAOKA
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Patent number: 10860251Abstract: A semiconductor memory device includes a first plane including a memory cell array, a second plane including a memory cell array, a control circuit configured to control operations performed on the first and second planes separately and independently, and first register for storing a condition value related to a condition of an operation to be performed on a plane. When a first command to store a first condition value in a first address of the first register is received, the control circuit specifies a plane to which the first address has been allocated. When the first plane is specified by the first address, the control circuit determines whether the first plane is in a command receivable state. Then, when the control circuit determines that the first plane is in the command receivable state, the control circuit stores the first condition value in the first address of the first register.Type: GrantFiled: February 26, 2019Date of Patent: December 8, 2020Assignee: Toshiba Memory CorporationInventors: Masaki Fujiu, Toshihiro Suzuki, Mitsuhiro Abe
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Publication number: 20190391758Abstract: A semiconductor memory device includes a first plane including a memory cell array, a second plane including a memory cell array, a control circuit configured to control operations performed on the first and second planes separately and independently, and first register for storing a condition value related to a condition of an operation to be performed on a plane. When a first command to store a first condition value in a first address of the first register is received, the control circuit specifies a plane to which the first address has been allocated. When the first plane is specified by the first address, the control circuit determines whether the first plane is in a command receivable state. Then, when the control circuit determines that the first plane is in the command receivable state, the control circuit stores the first condition value in the first address of the first register.Type: ApplicationFiled: February 26, 2019Publication date: December 26, 2019Inventors: Masaki FUJIU, Toshihiro SUZUKI, Mitsuhiro ABE
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Patent number: 9811493Abstract: According to one embodiment, a semiconductor device includes an input/output circuit. An input/output circuit includes first to third circuits. The first circuit transmits one of first to third data to the second circuit. The second circuit outputs the data, in a first-in-first-out (FIFO) format. The third circuit transmits first clock signal to the first circuit when the first circuit outputs one of the first and second data. When the one of the first and second data is read, the second circuit receives the one of the first and second data in response to the first clock signal within a period until a first signal is received. When the third data is read, the second circuit receives the third data in response to a second clock signal within the period.Type: GrantFiled: September 2, 2015Date of Patent: November 7, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Masatsugu Kojima, Mitsuhiro Abe
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Publication number: 20160350253Abstract: According to one embodiment, a semiconductor device includes an input/output circuit. An input/output circuit includes first to third circuits. The first circuit transmits one of first to third data to the second circuit. The second circuit outputs the data, in a first-in-first-out (FIFO) format. The third circuit transmits first clock signal to the first circuit when the first circuit outputs one of the first and second data. When the one of the first and second data is read, the second circuit receives the one of the first and second data in response to the first clock signal within a period until a first signal is received. When the third data is read, the second circuit receives the third data in response to a second clock signal within the period.Type: ApplicationFiled: September 2, 2015Publication date: December 1, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masatsugu KOJIMA, Mitsuhiro ABE
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Patent number: D786740Type: GrantFiled: February 25, 2016Date of Patent: May 16, 2017Assignee: HONDA MOTOR CO., LTD.Inventors: Mitsuhiro Abe, Kanna Goto, Takahiko Torii
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Patent number: D795744Type: GrantFiled: February 25, 2016Date of Patent: August 29, 2017Assignee: HONDA MOTOR CO., LTDInventors: Ken Sahara, Mitsuhiro Abe
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Patent number: D874348Type: GrantFiled: March 8, 2018Date of Patent: February 4, 2020Assignee: HONDA MOTOR CO., LTD.Inventors: Mitsuhiro Abe, Kanna Goto, Takahiko Torii
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Patent number: D998505Type: GrantFiled: January 20, 2022Date of Patent: September 12, 2023Assignee: HONDA MOTOR CO., LTD.Inventor: Mitsuhiro Abe
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Patent number: D1001026Type: GrantFiled: January 20, 2022Date of Patent: October 10, 2023Assignee: HONDA MOTOR CO., LTD.Inventor: Mitsuhiro Abe
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Patent number: D1001696Type: GrantFiled: January 20, 2022Date of Patent: October 17, 2023Assignee: HONDA MOTOR CO., LTD.Inventor: Mitsuhiro Abe
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Patent number: D1015250Type: GrantFiled: January 20, 2022Date of Patent: February 20, 2024Assignee: HONDA MOTOR CO., LTD.Inventor: Mitsuhiro Abe
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Patent number: D1024374Type: GrantFiled: January 20, 2022Date of Patent: April 23, 2024Assignee: HONDA MOTOR CO., LTD.Inventor: Mitsuhiro Abe