Patents by Inventor Mitsuhiro Abe

Mitsuhiro Abe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100099277
    Abstract: An embodiment of an electrical connecting apparatus comprises an electrical insulating plate, an elastic plate made of an electrical insulating material arranged on the electrical insulating plate, a sheet-like conductive plate arranged on the elastic plate, and first and second contacts. The conductive plate comprises a hole area having at least one first hole portion allowing the probe tip portion of the first contact to abut to the conductive plate and a plurality of second hole portions not allowing the probe tip portions of the second contacts to abut thereon regardless of whether or not overdriving acts on the contacts.
    Type: Application
    Filed: October 16, 2009
    Publication date: April 22, 2010
    Applicant: Kabushiki Kaisha Nihon Micronics
    Inventors: Eichi OSATO, Yoshihito Goto, Mitsuhiro Abe
  • Publication number: 20090186841
    Abstract: This invention relates to novel aminoglycoside antibiotics, which have potent antimicrobial activity against bacteria, which induce infectious diseases, particularly MRSA, and has no significant nephrotoxicity, and process for producing them. More particularly, the present invention relates to compounds represented by formula (Ia) or their pharmacologically acceptable salts or solvates, or their diastereomer mixtures, antimicrobial agents comprising them, and a process for producing them.
    Type: Application
    Filed: June 1, 2007
    Publication date: July 23, 2009
    Inventors: Yoshihiko Kobayashi, Yoshihisa Akiyama, Takeshi Murakami, Nobuto Minowa, Masaki Tsushima, Yukiko Hiraiwa, Shoichi Murakami, Mitsuhiro Abe, Kazushige Sasaki, Shigeru Hoshiko, Toshiaki Miyake, Yoshiaki Takahashi, Daishiro Ikeda
  • Patent number: 6938267
    Abstract: On a replica substrate 1a, a reflection layer 11, a first dielectric layer 12 made of ZnS—SiO2, a recording layer 13 made of a phase change type recording material, and a second dielectric layer 14 made of ZnS—SiO2 are successively formed. In addition, a reaction protection layer 15 made of Si3N4 or SiO2 is formed on the second dielectric layer 14. As a result, an information signal portion 1c is composed. A light transmissivity sheet is formed through an adhesive layer so that the light transmissivity sheet coats an information signal portion 1c. As a result, a light transmission layer is composed. When the reaction protection layer 15 is not formed, a reaction protection resin layer made of an ultraviolet ray setting resin is formed so that the reaction protection resin layer coats the information signal portion 1c.
    Type: Grant
    Filed: June 26, 2002
    Date of Patent: August 30, 2005
    Assignee: Sony Corporation
    Inventors: Minoru Kikuchi, Yoshio Shirai, Mitsuhiro Abe, Toru Abiko
  • Patent number: 6731561
    Abstract: A semiconductor memory includes a group of memory cells arrayed in a matrix, memory cell electric power source lines configured to connect the respective memory cells arrayed in a direction of rows of the group of memory cells of each of the rows, two electric power source terminals configured to be mutually independent, and switches configured to be connected between the memory cell electric power source lines and the two electric power source terminals respectively, to be controlled to turn ON/OFF by a inversion logic operation based on a test mode switching signal for switching to and from a test mode and a normal operation mode, and to connect the memory cell power source line to either of the two electric power source terminals according to the ON/OFF control.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: May 4, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsuhiro Abe, Kenta Kaneeda, Hiroo Ota, Hideo Niki
  • Publication number: 20040032823
    Abstract: On a replica substrate la, a reflection layer 11, a first dielectric layer 12 made of ZnS—SiO2, a recording layer 13 made of a phase change type recording material, and a second dielectric layer 14 made of ZnS—SiO2 are successively formed. In addition, a reaction protection layer 15 made of Si3N4 or SiO2 is formed on the second dielectric layer 14. As a result, an information signal portion 1c is composed. A light transmissivity sheet is formed through an adhesive layer so that the light transmissivity sheet coats an information signal portion 1c. As a result, a light transmission layer is composed. When the reaction protection layer 15 is not formed, a reaction protection resin layer made of an ultraviolet ray setting resin is formed so that the reaction protection resin layer coats the information signal portion 1c.
    Type: Application
    Filed: August 11, 2003
    Publication date: February 19, 2004
    Inventors: Minoru Kikuchi, Yoshio Shirai, Mitsuhiro Abe, Toru Abiko
  • Publication number: 20030040531
    Abstract: An objective of the present invention is to provide an agent that is clinically effective in the treatment or prevention of reperfusion injury. The agent for use in the treatment or prevention of reperfusion injury according to the present invention comprises an integrin &agr;v&bgr;3 antagonist, a pharmaceutically acceptable salt thereof, or a solvate thereof as active ingredient.
    Type: Application
    Filed: July 25, 2002
    Publication date: February 27, 2003
    Inventors: Kazuyuki Fujishima, Shoichi Murakami, Mikio Yamamoto, Mitsuhiro Abe, Minoru Ishikawa, Shokichi Ouchi, Keiichi Ajito
  • Publication number: 20020176306
    Abstract: A semiconductor memory includes a group of memory cells arrayed in a matrix, memory cell electric power source lines configured to connect the respective memory cells arrayed in a direction of rows of the group of memory cells of each of the rows, two electric power source terminals configured to be mutually independent, and switches configured to be connected between the memory cell electric power source lines and the two electric power source terminals respectively, to be controlled to turn ON/OFF by a inversion logic operation based on a test mode switching signal for switching to and from a test mode and a normal operation mode, and to connect the memory cell power source line to either of the two electric power source terminals according to the ON/OFF control.
    Type: Application
    Filed: March 15, 2002
    Publication date: November 28, 2002
    Inventors: Mitsuhiro Abe, Kenta Kaneeda, Hiroo Ota, Hideo Niki
  • Patent number: 6037638
    Abstract: The gates 31, 32, 33 and 34 of a pair of driver transistors Q1, Q2 and a pair of address-selecting transistors Q3, Q4 are arranged so as to be perpendicular to bit lines BL, /BL. The drain regions of the driver transistors Q1, Q2 forming a flip-flop are arranged point-symmetrically around an element isolating region. The source regions of the driver transistors Q1, Q2 are arranged point-symmetrically. Similarly, the address-selecting transistors Q3, Q4 are arranged point-symmetrically. An upper wiring layer connected to two gates of the transistors are arranged so as to be perpendicular to the bit lines BL, /BL. Two Vss lines are formed in the same layer as that for the bit lines BL, /BL and arranged on both sides of the bit lines BL, /BL in parallel thereto. The Vss lines are connected to the source regions of the driver transistors.
    Type: Grant
    Filed: March 4, 1998
    Date of Patent: March 14, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsuhiro Abe, Yoichi Suzuki, Makoto Segawa
  • Patent number: 5556647
    Abstract: An encapsulation mold includes a pot for heating resin inserted therein, a plunger, movably arranged in the pot, for extruding the resin from a bottom of the pot, and first and second retainer plates. One of the retainer plates includes a plurality of package portions, connected to the runners, for encapsulating electric elements with the resin by inserting the resin into the package portions, a cull portion, arranged at the bottom of the pot, for uniformly extruding the resin from the pot, and runners, connecting the cull portion to the package portions, for feeding the resin extruded from the pot by the plunger to the package portions through the runners. The runners have longitudinal projections provided along a flowing direction of the resin at a central part of each of the runners.
    Type: Grant
    Filed: December 7, 1994
    Date of Patent: September 17, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mitsuhiro Abe, Mitsuo Yamada
  • Patent number: 5349136
    Abstract: A mold tool for forming an electronic component having a semiconductor chip sealed on a supporting member by a resin-molded package, includes an upper mold having an upper cavity and a lower mold having a lower cavity, the package being molded in the cavities. Upper and lower gates are arranged at opposing surfaces of the molds and symmetrically formed with respect to a parting face of the mold tool to connect with the cavities. A method for forming the component includes the steps of inserting the supporting member with the chip in the cavities of the molds of the mold tool, clamping the molds, injecting molten resin into the cavities of the clamped molds through the upper and lower gates, cooling the molten resin in the cavities, and separating the molds from each other and removing the component from the cavities.
    Type: Grant
    Filed: February 10, 1993
    Date of Patent: September 20, 1994
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mitsuhiro Abe, Nakanishi Itsuto, Ariyoshi Hideho, Asao Iguchi
  • Patent number: 4299104
    Abstract: A method of controlling roll eccentricity of a rolling mill is disclosed, in which a component of a rolling load variation which is due to eccentricities of an upper and a lower backup rolls of the rolling mill is obtained as a first eccentricity compensation signal by removing a rolling load variation component due to a variation of thickness of a material to be rolled from a rolling load variation occurred during the rolling operation, a rolling load variation value due to the roll eccentricity of the backup rolls is obtained from a rolling load variation occurred during rotations of work rolls which are in contact with each other under a load and is memorized as a second roll eccentricity compensation signal, a first signal is obtained by multiplying the first roll eccentricity compensation signal with a coefficient which is larger than 0 and smaller than 1, a second signal is obtained by multiplying the second roll eccentricity compensation signal with another coefficient which is larger than 0 and smalle
    Type: Grant
    Filed: February 21, 1980
    Date of Patent: November 10, 1981
    Assignee: Mitsubishi Jukogyo Kabushiki Kaisha
    Inventors: Yasunobu Hayama, Kuniaki Tanouchi, Mitsuhiro Abe, Katsuhiro Ohkura