Patents by Inventor Mitsuhiro Horikawa

Mitsuhiro Horikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070155115
    Abstract: A method according to the present invention includes forming a silicon nitride film on a lower electrode, oxidizing the silicon nitride film, and forming a dielectric film including aluminum on the oxidized silicon nitride film.
    Type: Application
    Filed: December 14, 2006
    Publication date: July 5, 2007
    Applicant: ELPIDA MEMORY INC.
    Inventor: Mitsuhiro Horikawa
  • Publication number: 20070148896
    Abstract: A semiconductor device includes memory cells each having an MISFET for memory selection formed on one major surface of a semiconductor substrate and a capacitive element comprised of a lower electrode electrically connected at a bottom portion to one of a source and drain of the MISFET for memory selection via a first metal layer and an upper electrode formed on the lower electrode via a capacitive insulating film. The lower electrode has a thickness of 30 nm or greater at the bottom portion thereof. Sputtering with a high ionization ratio and high directivity, such as PCM, is adapted to the formation of the lower electrode to make only the bottom portion of a capacitor thicker.
    Type: Application
    Filed: November 27, 2006
    Publication date: June 28, 2007
    Inventors: Yoshitaka Nakamura, Hidekazu Goto, Isamu Asano, Mitsuhiro Horikawa, Keiji Kuroki, Hiroshi Sakuma, Kenichi Koyanagi, Tsuyoshi Kawagoe
  • Patent number: 7224016
    Abstract: A semiconductor device includes memory cells each having an MISFET for memory selection formed on one major surface of a semiconductor substrate and a capacitive element comprised of a lower electrode electrically connected at a bottom portion to one of a source and drain of the MISFET for memory selection via a first metal layer and an upper electrode formed on the lower electrode via a capacitive insulating film. The lower electrode has a thickness of 30 nm or greater at the bottom portion thereof. Sputtering with a high ionization ratio and high directivity, such as PCM, is adapted to the formation of the lower electrode to make only the bottom portion of a capacitor thicker.
    Type: Grant
    Filed: February 13, 2004
    Date of Patent: May 29, 2007
    Assignees: Elpida Memory, Inc., Hitachi ULSI Systems, Co., Ltd., Hitachi Ltd.
    Inventors: Yoshitaka Nakamura, Hidekazu Goto, Isamu Asano, Mitsuhiro Horikawa, Keiji Kuroki, Hiroshi Sakuma, Kenichi Koyanagi, Tsuyoshi Kawagoe
  • Publication number: 20040248362
    Abstract: A semiconductor device includes memory cells each having an MISFET for memory selection formed on one major surface of a semiconductor substrate and a capacitive element comprised of a lower electrode electrically connected at a bottom portion to one of a source and drain of the MISFET for memory selection via a first metal layer and an upper electrode formed on the lower electrode via a capacitive insulating film. The lower electrode has a thickness of 30 nm or greater at the bottom portion thereof. Sputtering with a high ionization ratio and high directivity, such as PCM, is adapted to the formation of the lower electrode to make only the bottom portion of a capacitor thicker.
    Type: Application
    Filed: February 13, 2004
    Publication date: December 9, 2004
    Applicants: ELPIDA MEMORY, INC., Hitachi ULSI Systems, Co., Ltd., HITACHI LTD.
    Inventors: Yoshitaka Nakamura, Hidekazu Goto, Isamu Asano, Mitsuhiro Horikawa, Keiji Kuroki, Hiroshi Sakuma, Kenichi Koyanagi, Tsuyoshi Kawagoe
  • Patent number: 6562733
    Abstract: There is prepared a wafer (10) having a gettering capability such as PBS wafer having deposition of polysilicon on its back surface thereof, IG wafer containing oxygen precipitates. An element separation silicon oxide film (2) is formed on the wafer (10), and a first silicon oxide film (3) is formed on the wafer (10). Then the wafer (10) is gradually cooled to a low temperature, or the wafer (10) is cooled to a low temperature and then kept at the low temperature for a fixed time. Thereafter, the first silicon oxide film (3) is removeed from the wafer (10) and then the wafer (30) is cleaned. Thereafter, a gate silicon oxide film (4) and a gate electrode (5) are formed. Subsequently, ion implantation to form a source (6) and a drain (7) and a heat treatment to activate implanted impurities are performed to form a basic MOS transistor.
    Type: Grant
    Filed: September 30, 1998
    Date of Patent: May 13, 2003
    Assignee: NEC Corporation
    Inventor: Mitsuhiro Horikawa
  • Patent number: 6372611
    Abstract: In a method of manufacturing a semiconductor device, a first polysilicon film is formed on a surface of a semiconductor substrate for a semiconductor element to be formed thereon. Ion implantation is performed in such a manner that impurity ions are implanted into the semiconductor substrate surface through the first polysilicon film. The semiconductor substrate is heated to a first temperature after the step of performing ion implantation. Then, the semiconductor substrate is gradually cooled with a predetermined cooling rate at least from a second temperature to a third temperature while the semiconductor substrate is cooled from the first temperature. The second and third temperatures are lower than the first temperature. Subsequently, the polysilicon film is removed after the gradually cooling step.
    Type: Grant
    Filed: January 14, 1998
    Date of Patent: April 16, 2002
    Assignee: NEC Corporation
    Inventor: Mitsuhiro Horikawa
  • Publication number: 20020037632
    Abstract: There is prepared a wafer (10) having a gettering capability such as PBS wafer having deposition of polysilicon on the back surface thereof, IG wafer containing oxygen precipitates therein, or the like. An element separation silicon oxide film (2) is formed on the wafer (10), and a first silicon oxide film (3) is formed on the wafer (10). Then the wafer (10) is gradually cooled to a low temperature, or the wafer (10) is cooled to a low temperature and then kept at the low temperature for a fixed time. Thereafter, the first silicon oxide film (3) is removeed from the wafer (10) and then the wafer (30) is cleaned. Thereafter, a gate silicon oxide film (4) and a gate electrode (5) are formed. Subsequently, ion implantation to form a source (6) and a drain (7) and a heat treatment to activate implanted impurities are performed to form a basic MOS transistor.
    Type: Application
    Filed: September 30, 1998
    Publication date: March 28, 2002
    Inventor: MITSUHIRO HORIKAWA
  • Patent number: 6300680
    Abstract: A semiconductor substrate is provided which maintains its gettering capabilities throughout the manufacturing process of a semiconductor device and which prevents previously gettered contaminating impurities from being released again into an operating region of a semiconductor device. The semiconductor substrate includes a silicon substrate, a polysilicon layer, and a high density boron layer. The silicon substrate has a first main surface and a second main surface opposed to the first main surface, and the silicon substrate is used to form a semiconductor device at least indirectly on the first main surface. The polysilicon film is formed at least indirectly on the second main surface, and the high density boron layer is disposed between the silicon substrate and the polysilicon film. Also a ratio of a highest boron density value in the high density boron layer to a lowest boron density value in the silicon substrate is greater than or equal to approximately 100.
    Type: Grant
    Filed: May 7, 1998
    Date of Patent: October 9, 2001
    Assignee: NEC Corporation
    Inventors: Mitsuhiro Horikawa, Masahito Watanabe
  • Patent number: 6046095
    Abstract: On the back side of a base body, three layers of polysilicon layer are formed. These polysilicon layers contain boron. A boron concentration C.sub.B(1), C.sub.B(2) and C.sub.B(3) of the first, second and third polysilicon layers from the base body side have a relationship of C.sub.B(1) .ltoreq.C.sub.B(2) .ltoreq.C.sub.B(3). On the other hand, between the polysilicon layers, silicon oxide layers are formed respectively. Upon fabrication of a semiconductor device, at first, a gettering heat treatment is effected for the substrate under a given condition. Thus, contaminating impurity is captured at the grain boundary of polysilicon layers formed on the back side of the base body. Next, the polysilicon formed at the most back side is removed by etching. By this, contaminated impurity is removed from the semiconductor substrate.
    Type: Grant
    Filed: June 25, 1999
    Date of Patent: April 4, 2000
    Assignee: NEC Corporation
    Inventor: Mitsuhiro Horikawa
  • Patent number: 5973386
    Abstract: On the back side of a base body, three layers of polysilicon layer are formed. These polysilicon layers contain boron. A boron concentration C.sub.B(1), C.sub.B(2) and C.sub.B(3) of the first, second and third polysilicon layers from the base body side have a relationship of C.sub.B(1) .ltoreq.C.sub.B(2) .ltoreq.C.sub.B(3). On the other hand, between the polysilicon layers, silicon oxide layers are formed respectively. Upon fabrication of a semiconductor device, at first, a gettering heat treatment is effected for the substrate under a given condition. Thus, contaminating impurity is captured at the grain boundary of polysilicon layers formed on the back side of the base body. Next, the polysilicon formed at the most back side is removed by etching. By this, contaminated impurity is removed from the semiconductor substrate.
    Type: Grant
    Filed: February 12, 1997
    Date of Patent: October 26, 1999
    Assignee: NEC Corporation
    Inventor: Mitsuhiro Horikawa
  • Patent number: 5062095
    Abstract: An actuator rotatable about a support shaft rectilinearly movable along axis of a shaft and rotatably movable about the shaft includes a cylindrical magnet extending about the shaft. The cylindrical magnet has a plurality of poles in the radial direction and magnetized boundaries between poles of opposite polarity extending in a circumferential direction of the magnet and extending in an axial direction of the magnet. A plurality of yokes are provided to define magnetic poles coupled in facing relationship with the magnetic boundaries of a cylindrical magnet and having coils coupled thereto to define the magnetic poles.
    Type: Grant
    Filed: January 27, 1989
    Date of Patent: October 29, 1991
    Assignee: Seiko Epson Corporation
    Inventors: Mitsuhiro Horikawa, Hiroshi Ito, Tsugio Ide, Michio Yanagisawa, Tatsuya Shimoda, Koji Akioka