Patents by Inventor Mitsuhiro KAKEFU
Mitsuhiro KAKEFU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240321834Abstract: A semiconductor device having a semiconductor unit including: a first arm part that includes first and second semiconductor chips respectively having first and second main electrodes, a first circuit pattern on which the first and second semiconductor chips are disposed, a second circuit pattern, a first main current wire connecting the first main electrode and second circuit pattern, and a second main current wire connecting the second main electrode and the second circuit pattern; and a second arm part that includes third and fourth semiconductor chips respectively having third and fourth main electrodes and being disposed on the second circuit pattern, a third circuit pattern, a third main current wire connecting the third main electrode and the third circuit pattern, and a fourth main current wire connecting the fourth main electrode and the third circuit pattern. Each semiconductor chip is an IGBT or MOSFET.Type: ApplicationFiled: June 5, 2024Publication date: September 26, 2024Applicant: FUJI ELECTRIC CO., LTD.Inventors: Mitsuhiro KAKEFU, Hiroaki ICHIKAWA
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Patent number: 12033984Abstract: A semiconductor device including a semiconductor unit that has a first arm part, which includes: first and second semiconductor chips having first and second control electrodes on their front surfaces, a first circuit pattern where the first and second semiconductor chips are disposed, a second circuit pattern to which the first and second control electrodes are connected, and a first control wire electrically connecting the first and second control electrodes and the second circuit pattern sequentially in a direction; and a second arm part, which includes third and fourth semiconductor chips having third and fourth control electrodes on their front surfaces, a third circuit pattern where the third and fourth semiconductor chips are disposed, a fourth circuit pattern to which the third and fourth control electrodes are connected, and a second control wire electrically connecting the third and fourth control electrodes and the fourth circuit pattern sequentially in the direction.Type: GrantFiled: May 12, 2023Date of Patent: July 9, 2024Assignee: FUJI ELECTRIC CO., LTD.Inventors: Mitsuhiro Kakefu, Hiroaki Ichikawa
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Publication number: 20230282622Abstract: A semiconductor device including a semiconductor unit that has a first arm part, which includes: first and second semiconductor chips having first and second control electrodes on their front surfaces, a first circuit pattern where the first and second semiconductor chips are disposed, a second circuit pattern to which the first and second control electrodes are connected, and a first control wire electrically connecting the first and second control electrodes and the second circuit pattern sequentially in a direction; and a second arm part, which includes third and fourth semiconductor chips having third and fourth control electrodes on their front surfaces, a third circuit pattern where the third and fourth semiconductor chips are disposed, a fourth circuit pattern to which the third and fourth control electrodes are connected, and a second control wire electrically connecting the third and fourth control electrodes and the fourth circuit pattern sequentially in the direction.Type: ApplicationFiled: May 12, 2023Publication date: September 7, 2023Applicant: FUJI ELECTRIC CO., LTD.Inventors: Mitsuhiro KAKEFU, Hiroaki ICHIKAWA
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Patent number: 11688722Abstract: A semiconductor device, having a first semiconductor chip including a first side portion at a front surface thereof and a first control electrode formed in the first side portion, a second semiconductor chip including a second side portion at a front surface thereof and a second control electrode formed in the second side portion, a first circuit pattern, on which the first semiconductor chip and the second semiconductor chip are disposed, a second circuit pattern, and a first control wire electrically connecting the first control electrode, the second control electrode, and the second circuit pattern. The first side portion and the second side portion are aligned. The first control electrode and the second control electrode are aligned. The second circuit pattern are aligned with the first control electrode and the second control electrode.Type: GrantFiled: January 21, 2021Date of Patent: June 27, 2023Assignee: FUJI ELECTRIC CO., LTD.Inventors: Mitsuhiro Kakefu, Hiroaki Ichikawa
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Patent number: 11515292Abstract: A semiconductor device, having a first semiconductor chip including a first side portion at a front surface thereof and a first control electrode formed in the first side portion, a second semiconductor chip including a second side portion at a front surface thereof and a second control electrode formed in the second side portion, a first circuit pattern, on which the first semiconductor chip and the second semiconductor chip are disposed, a second circuit pattern, and a first control wire electrically connecting the first control electrode, the second control electrode, and the second circuit pattern. The first side portion and the second side portion are aligned. The first control electrode and the second control electrode are aligned. The second circuit pattern are aligned with the first control electrode and the second control electrode.Type: GrantFiled: August 27, 2020Date of Patent: November 29, 2022Assignee: FUJI ELECTRIC CO., LTD.Inventors: Mitsuhiro Kakefu, Hiroaki Ichikawa
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Publication number: 20210143132Abstract: A semiconductor device, having a first semiconductor chip including a first side portion at a front surface thereof and a first control electrode formed in the first side portion, a second semiconductor chip including a second side portion at a front surface thereof and a second control electrode formed in the second side portion, a first circuit pattern, on which the first semiconductor chip and the second semiconductor chip are disposed, a second circuit pattern, and a first control wire electrically connecting the first control electrode, the second control electrode, and the second circuit pattern. The first side portion and the second side portion are aligned. The first control electrode and the second control electrode are aligned. The second circuit pattern are aligned with the first control electrode and the second control electrode.Type: ApplicationFiled: January 21, 2021Publication date: May 13, 2021Applicant: FUJI ELECTRIC CO., LTD.Inventors: Mitsuhiro KAKEFU, Hiroaki ICHIKAWA
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Publication number: 20200395343Abstract: A semiconductor device, having a first semiconductor chip including a first side portion at a front surface thereof and a first control electrode formed in the first side portion, a second semiconductor chip including a second side portion at a front surface thereof and a second control electrode formed in the second side portion, a first circuit pattern, on which the first semiconductor chip and the second semiconductor chip are disposed, a second circuit pattern, and a first control wire electrically connecting the first control electrode, the second control electrode, and the second circuit pattern. The first side portion and the second side portion are aligned. The first control electrode and the second control electrode are aligned. The second circuit pattern are aligned with the first control electrode and the second control electrode.Type: ApplicationFiled: August 27, 2020Publication date: December 17, 2020Applicant: FUJI ELECTRIC CO., LTD.Inventors: Mitsuhiro KAKEFU, Hiroaki ICHIKAWA
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Patent number: 10535729Abstract: In a semiconductor device including a low lifetime region of a depth within a range on both sides sandwiching a p-n junction of a p-type semiconductor region bottom portion, the low lifetime region includes a central region that has a portion coinciding with the semiconductor region as seen from one main surface side and is selectively formed as far as the position of a contact end portion of a region of the coinciding portion with which the semiconductor region and a metal electrode are in contact, a peripheral region wherein the central region extends as far as the position of an outer peripheral end of the semiconductor region, and an expanded end portion region wherein the peripheral region extends as far as an outer peripheral end of the innermost of guard rings. Because of this, it is possible to reduce leakage current while maintaining high reverse recovery current resistance.Type: GrantFiled: April 24, 2018Date of Patent: January 14, 2020Assignee: FUJI ELECTRIC CO., LTD.Inventor: Mitsuhiro Kakefu
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Publication number: 20180240866Abstract: In a semiconductor device including a low lifetime region of a depth within a range on both sides sandwiching a p-n junction of a p-type semiconductor region bottom portion, the low lifetime region includes a central region that has a portion coinciding with the semiconductor region as seen from one main surface side and is selectively formed as far as the position of a contact end portion of a region of the coinciding portion with which the semiconductor region and a metal electrode are in contact, a peripheral region wherein the central region extends as far as the position of an outer peripheral end of the semiconductor region, and an expanded end portion region wherein the peripheral region extends as far as an outer peripheral end of the innermost of guard rings. Because of this, it is possible to reduce leakage current while maintaining high reverse recovery current resistance.Type: ApplicationFiled: April 24, 2018Publication date: August 23, 2018Applicant: FUJI ELECTRIC CO., LTD.Inventor: Mitsuhiro Kakefu
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Patent number: 10056501Abstract: Provided is a device with improved reverse-recovery immunity of a diode element. The device includes: a first conductivity-type drift layer; a second conductivity-type anode region provided in an upper portion of the drift layer; a second conductivity-type extraction region in contact with and surrounding the anode region; and a second conductivity-type field limiting ring region surrounding and separated from the extraction region at the upper portion of the drift layer, wherein the extraction region has a greater depth than the anode region and the field limiting ring region.Type: GrantFiled: December 27, 2016Date of Patent: August 21, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventor: Mitsuhiro Kakefu
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Patent number: 9985090Abstract: In a semiconductor device including a low lifetime region of a depth within a range on both sides sandwiching a p-n junction of a p-type semiconductor region bottom portion, the low lifetime region includes a central region that has a portion coinciding with the semiconductor region as seen from one main surface side and is selectively formed as far as the position of a contact end portion of a region of the coinciding portion with which the semiconductor region and a metal electrode are in contact, a peripheral region wherein the central region extends as far as the position of an outer peripheral end of the semiconductor region, and an expanded end portion region wherein the peripheral region extends as far as an outer peripheral end of the innermost of guard rings. Because of this, it is possible to reduce leakage current while maintaining high reverse recovery current resistance.Type: GrantFiled: December 11, 2013Date of Patent: May 29, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventor: Mitsuhiro Kakefu
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Publication number: 20170110596Abstract: Provided is a device with improved reverse-recovery immunity of a diode element. The device includes: a first conductivity-type drift layer; a second conductivity-type anode region provided in an upper portion of the drift layer; a second conductivity-type extraction region in contact with and surrounding the anode region; and a second conductivity-type field limiting ring region surrounding and separated from the extraction region at the upper portion of the drift layer, wherein the extraction region has a greater depth than the anode region and the field limiting ring region.Type: ApplicationFiled: December 27, 2016Publication date: April 20, 2017Applicant: FUJI ELECTRIC CO., LTD.Inventor: Mitsuhiro KAKEFU
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Patent number: 9040362Abstract: A method of manufacturing a MOS type semiconductor device, includes, before forming a semiconductor functional structure including a necessary MOS gate structure on one principal surface of a silicon semiconductor substrate, in the order recited, a first step of heating the silicon semiconductor substrate in an oxygen-containing atmosphere under heat treatment conditions including a heat treatment temperature of higher than 1,280° C. and a heat treatment time necessary for introducing oxygen up to a solid solution limit concentration in the silicon semiconductor substrate as a whole body; and a second step of holding the silicon semiconductor substrate at a specified temperature in a range from 1,000° C. to 1,200° C. The method achieves small turn-off loss and little variation of ON voltages without controlling a collector layer to a lower concentration than the conventional technology.Type: GrantFiled: October 10, 2014Date of Patent: May 26, 2015Assignee: FUJI ELECTRIC CO., LTD.Inventor: Mitsuhiro Kakefu
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Publication number: 20150126000Abstract: A method of manufacturing a MOS type semiconductor device, includes, before forming a semiconductor functional structure including a necessary MOS gate structure on one principal surface of a silicon semiconductor substrate, in the order recited, a first step of heating the silicon semiconductor substrate in an oxygen-containing atmosphere under heat treatment conditions including a heat treatment temperature of higher than 1,280° C. and a heat treatment time necessary for introducing oxygen up to a solid solution limit concentration in the silicon semiconductor substrate as a whole body; and a second step of holding the silicon semiconductor substrate at a specified temperature in a range from 1,000° C. to 1,200° C. The method achieves small turn-off loss and little variation of ON voltages without controlling a collector layer to a lower concentration than the conventional technology.Type: ApplicationFiled: October 10, 2014Publication date: May 7, 2015Applicant: FUJI ELECTRIC CO., LTD.Inventor: Mitsuhiro KAKEFU
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Publication number: 20150108539Abstract: A fabrication method of a semiconductor device includes forming a mask insulating film having a specified thickness on the top surface of an n-type semiconductor substrate, forming an opening at a specified position in the mask insulating film, carrying out ion implantation with p-type impurity ions onto the top surface, removing a layer portion formed in the mask insulating film with the p-type impurities included by the ion implantation, and carrying out heat treatment to diffuse the p-type impurities implanted into the n-type semiconductor substrate from the opening to a depth, thereby forming the p-type isolation region.Type: ApplicationFiled: September 12, 2014Publication date: April 23, 2015Inventor: Mitsuhiro KAKEFU
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Publication number: 20140159192Abstract: In a semiconductor device including a low lifetime region of a depth within a range on both sides sandwiching a p-n junction of a p-type semiconductor region bottom portion, the low lifetime region includes a central region that has a portion coinciding with the semiconductor region as seen from one main surface side and is selectively formed as far as the position of a contact end portion of a region of the coinciding portion with which the semiconductor region and a metal electrode are in contact, a peripheral region wherein the central region extends as far as the position of an outer peripheral end of the semiconductor region, and an expanded end portion region wherein the peripheral region extends as far as an outer peripheral end of the innermost of guard rings. Because of this, it is possible to reduce leakage current while maintaining high reverse recovery current resistance.Type: ApplicationFiled: December 11, 2013Publication date: June 12, 2014Applicant: FUJI ELECTRIC CO., LTD.Inventor: Mitsuhiro KAKEFU
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Publication number: 20140117406Abstract: A reverse blocking IGBT is disclosed in which a lifetime control region formed by helium ion irradiation is selectively provided in a region within a range approximately corresponding to the planar pattern of a p-type base region in the direction along the principal surface of a silicon semiconductor substrate of n-type and within a range from the upward vicinity to the downward vicinity of the p-n junction on the bottom of the p-type base region in the direction of the depth of the silicon semiconductor substrate. This can provide a reverse blocking MOS semiconductor device capable of further decreasing a reverse leakage current less than the current in a previous device while making the influence on an on-state current small.Type: ApplicationFiled: October 16, 2013Publication date: May 1, 2014Applicant: FUJI ELECTRIC CO., LTD.Inventor: Mitsuhiro KAKEFU
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Patent number: D884662Type: GrantFiled: November 7, 2018Date of Patent: May 19, 2020Assignee: FUJI ELECTRIC CO., LTD.Inventors: Taichi Itoh, Hiroaki Ichikawa, Mitsuhiro Kakefu, Akio Yamano, Takuya Yamamoto