Patents by Inventor Mitsuhiro Yamamoto

Mitsuhiro Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110289450
    Abstract: A method and apparatus for displaying batch execution data of an industrial plant configured for performing a plurality of batch executions. The method comprises selecting a first level element in a first level window; and displaying in a second level window all second level elements comprised by the selected first level element, the second level window being displayed within the first level window directly beneath the selected first level element without obscuring any other first level element in the first level window.
    Type: Application
    Filed: May 21, 2010
    Publication date: November 24, 2011
    Applicant: YOKOGAWA ELECTRIC CORPORATION
    Inventors: Hirofumi Takahashi, Mitsuhiro Yamamoto
  • Publication number: 20110111995
    Abstract: In this grease composition, a grease produced by mixing at least one base oil selected from a mineral oil-type lubricant base oil, a synthetic lubricant base oil, and a biodegradable lubricant base oil with a thickener is compounded with a wax and water, and an additive such as a surfactant and a defoamer is optionally compounded therewith. A soap containing a calcium sulfonate complex is used as the thickener. A carnauba wax is preferably used as the wax. Since this grease composition is mainly composed of a grease and a wax, the grease composition extremely facilities its removal operation after application, is environmentally friendly, and has extremely excellent anti-corrosion performance. When the grease composition is used by being applied to a base material of an object to be welded, an effect of preventing the adhesion of welding spatters can be obtained.
    Type: Application
    Filed: October 27, 2008
    Publication date: May 12, 2011
    Applicant: HITACHI CONSTRUCTION MACHINERY CO., LTD.
    Inventors: Hideki Akita, Shigeyuki Sakurai, Osamu Gokita, Shinichi Sekido, Masafumi Senzaki, Yasuchika Nagai, Mitsuhiro Yamamoto, Tooru Nakajima, Mitsuru Komachi, Hiroshi Nishimura, Jun Araki
  • Patent number: 7902856
    Abstract: An exemplary aspect of the invention is to conduct delay tests under actual operating conditions for a semiconductor integrated circuit including multiple logic circuits operating based on clocks of different frequencies, without causing any inconveniences when a test clock is set to a high-frequency side or a low-frequency side. The semiconductor integrated circuit includes: a first logic block that operates based on a first clock; a second logic block that operates based on a second clock having a frequency different from that of the first clock; and a test circuit connected between the first logic block and the second logic block. The test circuit outputs an output of the first logic block set as a test target, without passing through the second logic block, and transmits an input value received without being passed through the first logic circuit, to the second logic circuit set as a test target.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: March 8, 2011
    Assignee: RENESAS Electronics Corporation
    Inventor: Mitsuhiro Yamamoto
  • Publication number: 20100207662
    Abstract: An exemplary aspect of the invention is to conduct delay tests under actual operating conditions for a semiconductor integrated circuit including multiple logic circuits operating based on clocks of different frequencies, without causing any inconveniences when a test clock is set to a high-frequency side or a low-frequency side. The semiconductor integrated circuit includes: a first logic block that operates based on a first clock; a second logic block that operates based on a second clock having a frequency different from that of the first clock; and a test circuit connected between the first logic block and the second logic block. The test circuit outputs an output of the first logic block set as a test target, without passing through the second logic block, and transmits an input value received without being passed through the first logic circuit, to the second logic circuit set as a test target.
    Type: Application
    Filed: February 12, 2010
    Publication date: August 19, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Mitsuhiro Yamamoto
  • Patent number: 7747621
    Abstract: The invention provides a system that associates data files with one another effectively to visually represent a relation among the data files and allows a user to easily understand relationship of contents of the data files. The system determines whether there is a parent data file for a selected retrieval object data file with reference to a contract association table and, if the parent data file is present, changes the retrieval object to the parent data file and repeats the processing. If the parent data file is not present, the system stores a present retrieval object data file as display data, that is, store a top data file as display data. Then, the system retrieves all data files associated with the top data file, stores the data files as display data, generates a relation diagram of the data files, and transmits the relation diagram to a user terminal.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: June 29, 2010
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hisashi Sato, Yoshitaka Masuzawa, Mitsuhiro Yamamoto, Katsuya Yamashita, Hideyuki Fujiwara, Shigeto Nakayama
  • Patent number: 7446759
    Abstract: An object of this array substrate for a flat display device is to eliminate display unevenness caused by the inequality of parasitic capacitances of switches of signal line switch circuits. Electrode patterns (P) which connects the gate electrodes of the switches (ASW) to any one of a plurality of switch control signal lines (ASWL1 and ASWL2) are formed so as to each two-dimensionally overlap all of the switch control signal lines ASWL and to have substantially identical shapes, thus equalizing the areas of the electrode patterns (P).
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: November 4, 2008
    Assignee: Toshiba Matsushita Display Technology Co., Ltd.
    Inventor: Mitsuhiro Yamamoto
  • Patent number: 7391053
    Abstract: In order to make it possible to easily detect an electrical defect by using an array tester, the present inspection substrate includes: plural scan lines and plural signal lines; plural storage capacitor lines arranged in parallel to the scan lines; storage capacitor elements, each of which uses a part of the storage capacitor line as one of electrodes thereof; storage capacitor upper electrodes formed of the same layer as that for the signal lines and electrically connected to the storage capacitor elements; switching elements arranged on intersection points of the signal lines and the scan lines and electrically connected to the storage capacitor elements; and dummy wiring lines formed by use of at least one of two types of metals constituting electrodes of the switching elements, and electrically connected to any of the scan lines, the signal lines, the storage capacitor lines and the storage capacitor upper electrodes.
    Type: Grant
    Filed: May 5, 2005
    Date of Patent: June 24, 2008
    Assignee: Toshiba Matsushita Display Technology Co., Ltd.
    Inventors: Tetsuya Iizuka, Mitsuhiro Yamamoto, Hiroshi Tabatake
  • Publication number: 20060284643
    Abstract: A method for inspecting array substrates, which includes a first array substrate having first pads and first electrodes, and a second array substrate having second pads and second electrodes, the method comprising connecting the first pads to terminals formed an array of inspection pad groups and disposed in a predetermined arrangement, bringing probes with an arrangement corresponding to the predetermined arrangement into contact with the terminals, and supplying electric power to the first electrodes via the probes, thereby inspecting whether the first electrodes of the first array substrate is defective or not, and connecting the second pad to the terminals, bringing the probes, without changing the arrangement thereof, into contact with the terminals, and supplying electric power to the second electrodes via the probes, thereby inspecting whether the second electrodes of the second array substrate is defective or not.
    Type: Application
    Filed: August 28, 2006
    Publication date: December 21, 2006
    Inventors: Mitsuhiro Yamamoto, Masaki Miyatake
  • Publication number: 20060114202
    Abstract: An object of this array substrate for a flat display device is to eliminate display unevenness caused by the inequality of parasitic capacitances of switches of signal line switch circuits. Electrode patterns (P) which connects the gate electrodes of the switches (ASW) to any one of a plurality of switch control signal lines (ASWL1 and ASWL2) are formed so as to each two-dimensionally overlap all of the switch control signal lines ASWL and to have substantially identical shapes, thus equalizing the areas of the electrode patterns (P).
    Type: Application
    Filed: May 28, 2004
    Publication date: June 1, 2006
    Applicant: Toshiba Matsushita Display Technology Co., Ltd
    Inventor: Mitsuhiro Yamamoto
  • Publication number: 20060103416
    Abstract: A method of inspecting a substrate comprising forming the common terminal that is connected to a part of wirings formed in the first array region and a part of wirings formed in the second array region on the substrate, supplying an electric signal from the common terminal to both of the part of the wirings formed in the first array region and the part of the wirings formed in the second array region, thereby charging the pixel electrodes in the first and second array regions, and irradiating an electron beam to the charged pixel electrodes, and inspecting whether or not the pixel electrodes properly hold the electrical charge based on a data of a secondary electron emitted from the pixel electrodes.
    Type: Application
    Filed: December 6, 2005
    Publication date: May 18, 2006
    Inventors: Masaki Miyatake, Mitsuhiro Yamamoto
  • Publication number: 20060092679
    Abstract: An array substrate comprising a substrate on which a plurality of scanning lines and a plurality of signal lines are arranged so as to intersect each other, pixel sections formed on the substrate and including an auxiliary capacitor and a switching element which is located close to each of intersections of the scanning lines and the signal lines, a regulation pad group provided to supply or output a signal to the scanning lines and the signal lines, a line made of metal and formed inside the substrate and along a periphery thereof, and a mark formed within a width region of the line by extracting part of a metal portion.
    Type: Application
    Filed: December 6, 2005
    Publication date: May 4, 2006
    Inventors: Masaki Miyatake, Mitsuhiro Yamamoto
  • Patent number: 7020148
    Abstract: A data transferring apparatus includes a ring bus, which circularly transfers data by holding in a slot to one direction and a plurality of nodes connected to the ring bus. Each of the plurality of nodes includes a detector and a controller. The detector detects whether or not data destined for a self-node is held in a slot arrived to another node connected to an upstream side of the self-node. The controller captures the data destined for the self-node from the slot when the detector detects presence of the data destined for the self-node and the slot arrives to the self-node.
    Type: Grant
    Filed: November 14, 2000
    Date of Patent: March 28, 2006
    Assignee: NEC Electronics Corporation
    Inventor: Mitsuhiro Yamamoto
  • Publication number: 20050263810
    Abstract: In order to make it possible to easily detect an electrical defect by using an array tester, the present inspection substrate includes: plural scan lines and plural signal lines; plural storage capacitor lines arranged in parallel to the scan lines; storage capacitor elements, each of which uses a part of the storage capacitor line as one of electrodes thereof; storage capacitor upper electrodes formed of the same layer as that for the signal lines and electrically connected to the storage capacitor elements; switching elements arranged on intersection points of the signal lines and the scan lines and electrically connected to the storage capacitor elements; and dummy wiring lines formed by use of at least one of two types of metals constituting electrodes of the switching elements, and electrically connected to any of the scan lines, the signal lines, the storage capacitor lines and the storage capacitor upper electrodes.
    Type: Application
    Filed: May 5, 2005
    Publication date: December 1, 2005
    Applicant: Toshiba Matsushita Display Technology
    Inventors: Tetsuya Iizuka, Mitsuhiro Yamamoto, Hiroshi Tabatake
  • Publication number: 20050160109
    Abstract: The invention provides a system that associates data files with one another effectively to visually represent a relation among the data files and allows a user to easily understand relationship of contents of the data files. The system determines whether there is a parent data file for a selected retrieval object data file with reference to a contract association table and, if the parent data file is present, changes the retrieval object to the parent data file and repeats the processing. If the parent data file is not present, the system stores a present retrieval object data file as display data, that is, store a top data file as display data. Then, the system retrieves all data files associated with the top data file, stores the data files as display data, generates a relation diagram of the data files, and transmits the relation diagram to a user terminal.
    Type: Application
    Filed: December 16, 2004
    Publication date: July 21, 2005
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Hisashi Sato, Yoshitaka Masuzawa, Mitsuhiro Yamamoto, Katsuya Yamashita, Hideyuki Fujiwara, Shigeto Nakayama
  • Patent number: 6777109
    Abstract: A ceramic capacitor for operating at a suppressed self heat-generation and a low loss even in high voltage operating conditions, including a dielectric ceramic element assembly having two surfaces and made of a material selected from the group consisting of a dielectric composition of CaTiO3—La2O3—TiO2 system, a dielectric composition of CaTiO3—La2O3—TiO2—SrTiO3 system, a dielectric composition of SrTiO3—CaTiO3 system, a dielectric composition of SrTiO3—CaTiO3—Bi2O3—TiO2 system, a dielectric composition of SrTiO3—PbTiO3—PbTiO3 system, and a dielectric composition of SrTiO3—PbTiO3—Bi2/3TiO3—CaTiO3 system; and an electrode made mainly of Zn located on each of the two surfaces of the dielectric ceramic element.
    Type: Grant
    Filed: September 16, 2002
    Date of Patent: August 17, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mitsuaki Kimoto, Masanori Fujimura, Tokuji Nishino, Mitsuhiro Yamamoto
  • Publication number: 20030137797
    Abstract: A ceramic capacitor that works at a suppressed self heat-generation and a low loss even in the high voltage operating conditions.
    Type: Application
    Filed: September 16, 2002
    Publication date: July 24, 2003
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mitsuaki Kimoto, Masanori Fujimura, Tokuji Nishino, Mitsuhiro Yamamoto
  • Publication number: 20020059613
    Abstract: A display apparatus configured to add variations to displayed contents to prevent the user from getting bored and sufficiently utilize the characteristics of a display panel such as an organic EL display panel which excels in displaying a moving image. The display apparatus is suitable for use in an electronic equipment, and comprises a display panel for displaying images, a storage unit contained in the electronic equipment for storing display data representative of display images for display on the display panel, and a writing unit for writing display data into the storage device from the outside. In one embodiment, a device body is provided with a rewritable memory such as a flash memory to provide an environment in which previously provided data can be captured through the Internet, or images created by the user can be uniquely captured.
    Type: Application
    Filed: August 27, 2001
    Publication date: May 16, 2002
    Applicant: Pioneer Corporation and Pioneer System Technologies Corporation
    Inventors: Mitsuhiro Yamamoto, Kunio Toyoda, Ikuo Nagahata, Shoji Suenaga, Shuichi Mori
  • Patent number: 5978203
    Abstract: An electronic part such as a ceramic capacitor and a resistor used in various kinds of electric appliances has an apprehension that an electronic part element might be red-heated to be burnt when an abnormal current flows in spite of dielectric covering member, and therefore it has been impossible to supply a nonflammable electronic part having a stabilized performance. In the present invention, an electronic part is constructed such that since an electronic part element 8 such as a condenser or a resistor is put in a case 5 which in turn is nearly sealed to cut off the supply of oxygen, the electronic part is prevented from catching fire even if it generates heat, and since an opening 6 is formed in a portion of the case 5 or a sealing member 7 so as to allow the gas to be let out, when the electronic part generates heat to increase the pressure, the case 5 can be prevented from being ruptured. Accordingly, it is possible to provide a nonflammable electronic part having stabilized characteristics.
    Type: Grant
    Filed: April 2, 1997
    Date of Patent: November 2, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshihiro Kiyomura, Hiroshi Oishi, Katsutoshi Nakamatsu, Mitsuhiro Yamamoto
  • Patent number: 5756260
    Abstract: By using a polyamic acid ester comprising the following structural units (1a), (1b) and (1c) as a photosensitive resin and a sulfonamide compound or a specific glycol ether acetate as a stabilizer, a photo-sensitive resin composition excellent especially in viscosity stability can be obtained, and by using the above photosensitive resin and a specific developer, a relief pattern of high resolution can be formed.
    Type: Grant
    Filed: October 15, 1996
    Date of Patent: May 26, 1998
    Assignee: Sumitomo Bakelite Company Limited
    Inventors: Nobuyuki Sashida, Toshio Banba, Naoshige Takeda, Mitsuhiro Yamamoto
  • Patent number: 5742408
    Abstract: An image processing apparatus previously stores information on particular kinds of image, determines the degree of similarity between an input full-color image signal and the information on particular kinds of image, controls conditions for addition of a particular pattern previously stored according to a result of the determination, and outputs an image by adding or not adding the particular pattern to the full-color image signal according to the addition conditions.
    Type: Grant
    Filed: January 7, 1997
    Date of Patent: April 21, 1998
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masahiro Funada, Toshiyuki Kitamura, Mitsuhiro Yamamoto, Eiji Ohta