Patents by Inventor Mitsunobu Miyamoto
Mitsunobu Miyamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9520476Abstract: A semiconductor device (100A) includes a substrate (2), an oxide semiconductor layer (5) formed on the substrate (2), source and drain electrodes (6s, 6d) electrically connected to the oxide semiconductor layer (5), a first transparent electrode (7) electrically connected to the drain electrode (6d), a dielectric layer (8) formed on the source and drain electrodes (6s, 6d), and a second transparent electrode (9) formed on the dielectric layer (8). The upper and/or lower surface(s) of the first transparent electrode (7) contacts with a reducing insulating layer (8a) with the property of reducing an oxide semiconductor included in the oxide semiconductor layer (5). The second transparent electrode (9) overlaps at least partially with the first transparent electrode (7) via the dielectric layer (8). The oxide semiconductor layer (5) and the first transparent electrode (7) are formed out of the same oxide film.Type: GrantFiled: January 24, 2013Date of Patent: December 13, 2016Assignee: Sharp kabushiki KaishaInventors: Tadayoshi Miyamoto, Kazuatsu Ito, Shigeyasu Mori, Mitsunobu Miyamoto, Yasuyuki Ogawa, Makoto Nakazawa, Seiichi Uchida, Takuya Matsuo
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Patent number: 9379250Abstract: This semiconductor device (100A) includes: a substrate (2); a gate electrode (3) formed on the substrate (2); a gate insulating layer (4) formed over the gate electrode (3); an oxide semiconductor layer (5) formed on the gate insulating layer (4); source and drain electrodes (6s, 6d) electrically connected to the oxide semiconductor layer (5); a first transparent electrode (7) electrically connected to the drain electrode (6d); an interlayer insulating layer (8a) including portions formed on the source and drain electrodes (6s, 6d); and a second transparent electrode (9) formed on the interlayer insulating layer (8a). At least a portion of the second transparent electrode (9) overlaps with the first transparent electrode (7) with the interlayer insulating layer (8a) interposed between them. And the oxide semiconductor layer (5) and the first transparent electrode (7) are formed out of a same oxide film.Type: GrantFiled: June 12, 2013Date of Patent: June 28, 2016Assignee: Sharp Kabushiki KaishaInventors: Seiichi Uchida, Yasuyuki Ogawa, Tadayoshi Miyamoto, Kazuatsu Ito, Yutaka Takamaru, Makoto Nakazawa, Mitsunobu Miyamoto
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Patent number: 9373648Abstract: This semiconductor device (100A) includes: an oxide layer (15) which includes a semiconductor region (5) and a conductor region (7) that contacts with the semiconductor region; a source electrode (6s) and a drain electrode (6d) which are electrically connected to the semiconductor region; an insulating layer (11) formed on the source and drain electrodes; a transparent electrode (9) arranged to overlap at least partially with the conductor region with the insulating layer interposed between them; a source line (6a) formed out of the same conductive film as the source electrode; and a gate extended line (3a) formed out of the same conductive film as a gate electrode (3). The source line is electrically connected to the gate extended line via a transparent connecting layer (9a) which is formed out of the same conductive film as the transparent electrode.Type: GrantFiled: April 22, 2013Date of Patent: June 21, 2016Assignee: Sharp Kabushiki KaishaInventors: Yutaka Takamaru, Kazuatsu Ito, Tadayoshi Miyamoto, Mitsunobu Miyamoto, Makoto Nakazawa, Yasuyuki Ogawa, Seiichi Uchida, Shigeyasu Mori
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Patent number: 9337213Abstract: This semiconductor device (100) includes: a gate electrode (3); a gate insulating layer (4); an oxide layer (50) which is formed on the gate insulating layer (4) and which includes a first conductor region (55) and a first semiconductor region (51) that overlaps at least partially with the gate electrode (3) with the gate insulating layer (4) interposed between them; a source electrode (6s) formed to contact with the upper surface of the first semiconductor region (51) of the oxide layer (50); a drain electrode (6d) which is formed to contact with the upper surface of the first semiconductor region (51) of the oxide layer (50) and which is electrically connected to the first conductor region (55); and a conductive layer (60) which is formed in contact with the upper surface of the oxide layer (50) and which a plurality of holes (66) or notches.Type: GrantFiled: March 29, 2013Date of Patent: May 10, 2016Assignee: Sharp Kabushiki KaishaInventors: Kazuatsu Ito, Yutaka Takamaru, Tadayoshi Miyamoto, Mitsunobu Miyamoto, Makoto Nakazawa, Yasuyuki Ogawa, Seiichi Uchida, Shigeyasu Mori
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Patent number: 9276126Abstract: This semiconductor device (100A) includes: a substrate (1); a gate electrode (3) and a first transparent electrode (2) which are formed on the substrate (1); a first insulating layer (4) formed over the gate electrode (3) and the first transparent electrode (2); an oxide semiconductor layer (5) formed on the first insulating layer (4); source and drain electrodes (6s, 6d) electrically connected to the oxide semiconductor layer (5); and a second transparent electrode (7) electrically connected to the drain electrode (6d). At least a portion of the first transparent electrode (2) overlaps with the second transparent electrode (7) with the first insulating layer (4) interposed between them, and the oxide semiconductor layer (5) and the second transparent electrode (7) are formed out of the same oxide film.Type: GrantFiled: January 24, 2013Date of Patent: March 1, 2016Assignee: Sharp Kabushiki KaishaInventors: Tadayoshi Miyamoto, Kazuatsu Ito, Shigeyasu Mori, Mitsunobu Miyamoto, Yasuyuki Ogawa, Makoto Nakazawa, Seiichi Uchida, Takuya Matsuo
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Patent number: 9214533Abstract: This semiconductor device (100A) includes: a substrate (2); a gate electrode (3) formed on the substrate (2); a gate insulating layer (4) formed over the gate electrode (3); an oxide semiconductor layer (5) formed on the gate insulating layer (4); source and drain electrodes (6s, 6d) electrically connected to the oxide semiconductor layer (5); a first transparent electrode (7) electrically connected to the drain electrode (6d); an interlayer insulating layer (8) including a dielectric layer (8a) formed over the source and drain electrodes (6s, 6d); and a second transparent electrode (9) formed on the interlayer insulating layer (8). At least a portion of the second transparent electrode (9) overlaps with the first transparent electrode (7) with the dielectric layer (8a) interposed between them, and the oxide semiconductor layer (5) and the first transparent electrode (7) are formed out of the same oxide film.Type: GrantFiled: January 24, 2013Date of Patent: December 15, 2015Assignee: Sharp Kabushiki KaishaInventors: Tadayoshi Miyamoto, Kazuatsu Ito, Shigeyasu Mori, Mitsunobu Miyamoto, Yasuyuki Ogawa, Makoto Nakazawa, Takuya Matsuo, Seiichi Uchida
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Publication number: 20150316804Abstract: The present invention provides a conductive structure capable of sufficiently preventing connection failure between two conductive layers regardless of the diameter and depth of a contact hole, a method for producing the conductive structure, and a display device including the conductive structure. The conductive structure of the present invention includes, in the following sequence: a first conductive layer, at least one insulating layer, and a second conductive layer electrically connected to the first conductive layer, the first conductive layer including a protrusion that is disposed in an opening provided in the at least one insulating layer and is connected directly to the second conductive layer.Type: ApplicationFiled: December 20, 2013Publication date: November 5, 2015Applicant: Sharp Kabushiki KaishaInventor: Mitsunobu MIYAMOTO
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Publication number: 20150200303Abstract: This semiconductor device (100A) includes: a substrate (2); a gate electrode (3) formed on the substrate (2); a gate insulating layer (4) formed over the gate electrode (3); an oxide semiconductor layer (5) formed on the gate insulating layer (4); source and drain electrodes (6s, 6d) electrically connected to the oxide semiconductor layer (5); a first transparent electrode (7) electrically connected to the drain electrode (6d); an interlayer insulating layer (8a) including portions formed on the source and drain electrodes (6s, 6d); and a second transparent electrode (9) formed on the interlayer insulating layer (8a). At least a portion of the second transparent electrode (9) overlaps with the first transparent electrode (7) with the interlayer insulating layer (8a) interposed between them. And the oxide semiconductor layer (5) and the first transparent electrode (7) are formed out of a same oxide film.Type: ApplicationFiled: June 12, 2013Publication date: July 16, 2015Inventors: Seiichi Uchida, Yasuyuki Ogawa, Tadayoshi Miyamoto, Kazuatsu Ito, Yutaka Takamaru, Makoto Nakazawa, Mitsunobu Miyamoto
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Patent number: 9081243Abstract: A TFT substrate (100) is provided with TFTs disposed on a substrate (2), first insulating layers (24, 26) disposed above the TFTs, a lower layer transparent electrode (12) disposed above the first insulating layers (24, 26), a second insulating layer (28) covering the lower layer transparent electrode (12), and pixel electrodes (10) disposed on the second insulating layer (28), in which an auxiliary capacitance (Cs) is formed by means of the lower layer transparent electrode (12), the second insulating layer (28), and the pixel electrode (10). The TFT and the pixel electrode (10) are electrically connected via a contact hole (34) penetrating the first insulating layers (24, 26) and the second insulating layer (28). A connecting transparent electrode (14) is disposed within the contact hole (34).Type: GrantFiled: June 15, 2012Date of Patent: July 14, 2015Assignee: SHARP KABUSHIKI KAISHAInventors: Makoto Nakazawa, Mitsunobu Miyamoto
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Patent number: 9035303Abstract: This semiconductor device (100A) includes: a gate electrode (3) formed on a substrate (2); a gate insulating layer (4) formed on the gate electrode; an oxide layer (50) which is formed on the gate insulating layer and which includes a semiconductor region (51) and a conductor region (55); source and drain electrodes (6s, 6d) electrically connected to the semiconductor region; a protective layer (11) formed on the source and drain electrodes; and a transparent electrode (9) formed on the protective layer. At least part of the transparent electrode overlaps with the conductor region with the protective layer interposed between them. The upper surface of the conductor region contacts with a reducing insulating layer (61) with the property of reducing an oxide semiconductor included in the oxide layer. The reducing insulating layer is out of contact with the channel region of the semiconductor region.Type: GrantFiled: April 1, 2013Date of Patent: May 19, 2015Assignee: Sharp Kabushiki KaishaInventors: Tadayoshi Miyamoto, Kazuatsu Ito, Mitsunobu Miyamoto, Yutaka Takamaru
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Publication number: 20150129865Abstract: This semiconductor device (100A) includes: a gate electrode (3); a gate insulating layer (4); an oxide layer (50) which is formed over the gate insulating layer (4) and which includes a semiconductor region (51) and a first conductor region (55) that contacts with the semiconductor region (51) and where the semiconductor region (51) at least partially overlaps with the gate electrode (3) with the gate insulating layer (4) interposed between them; a protective layer (8b) covering the upper surface of the semiconductor region (51); source and drain electrodes (6s, 6d) electrically connected to the semiconductor region (51); and a transparent electrode (9) arranged so as to overlap at least partially with the first conductor region (55) with a dielectric layer interposed between them. The drain electrode (6d) contacts with the first conductor region (55).Type: ApplicationFiled: March 4, 2013Publication date: May 14, 2015Inventors: Tadayoshi Miyamoto, Kazuatsu Ito, Mitsunobu Miyamoto, Yutaka Takamaru
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Patent number: 9029209Abstract: A method of manufacturing a thin film transistor substrate (1) includes at least the steps of: forming a gate electrode (15) on an insulating substrate (10) by using a first photomask; forming a channel protective film (21) on an oxide semiconductor layer (13) so as to cover a channel region (C) by using a second photomask; forming a source electrode (19) on the oxide semiconductor layer (13) by using a third photomask; and forming a planarizing film (18) on an interlayer insulating film (17) by using a fourth photomask.Type: GrantFiled: October 11, 2011Date of Patent: May 12, 2015Assignee: Sharp Kabushiki KaishaInventor: Mitsunobu Miyamoto
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Patent number: 9023685Abstract: A semiconductor device including a semiconductor layer, a plurality of electrode portions each overlapping the semiconductor layer, and an insulating film placed between the plurality of electrode portions to lie on the semiconductor layer is fabricated. The fabrication method includes the steps of: forming an oxide semiconductor layer part of which is covered with the insulating film; forming a conductive material layer to cover the oxide semiconductor layer and the insulating film; forming the plurality of electrode portions from the conductive material layer by photolithography and plasma dry etching, to expose part of the oxide semiconductor layer from the plurality of electrode portions and the insulating film; and removing the part of the oxide semiconductor layer exposed from the plurality of electrode portions and the insulating film to form the semiconductor layer.Type: GrantFiled: February 22, 2012Date of Patent: May 5, 2015Assignee: Sharp Kabushiki KaishaInventor: Mitsunobu Miyamoto
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Publication number: 20150084039Abstract: This semiconductor device (100A) includes: an oxide layer (15) which includes a semiconductor region (5) and a conductor region (7) that contacts with the semiconductor region; a source electrode (6s) and a drain electrode (6d) which are electrically connected to the semiconductor region; an insulating layer (11) formed on the source and drain electrodes; a transparent electrode (9) arranged to overlap at least partially with the conductor region with the insulating layer interposed between them; a source line (6a) formed out of the same conductive film as the source electrode; and a gate extended line (3a) formed out of the same conductive film as a gate electrode (3). The source line is electrically connected to the gate extended line via a transparent connecting layer (9a) which is formed out of the same conductive film as the transparent electrode.Type: ApplicationFiled: April 22, 2013Publication date: March 26, 2015Inventors: Yutaka Takamaru, Kazuatsu Ito, Tadayoshi Miyamoto, Mitsunobu Miyamoto, Makoto Nakazawa, Yasuyuki Ogawa, Seiichi Uchida, Shigeyasu Mori
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Publication number: 20150069381Abstract: This semiconductor device (100A) includes: a gate electrode (3) formed on a substrate (2); a gate insulating layer (4) formed on the gate electrode; an oxide layer (50) which is formed on the gate insulating layer and which includes a semiconductor region (51) and a conductor region (55); source and drain electrodes (6s, 6d) electrically connected to the semiconductor region; a protective layer (11) formed on the source and drain electrodes; and a transparent electrode (9) formed on the protective layer. At least part of the transparent electrode overlaps with the conductor region with the protective layer interposed between them. The upper surface of the conductor region contacts with a reducing insulating layer (61) with the property of reducing an oxide semiconductor included in the oxide layer. The reducing insulating layer is out of contact with the channel region of the semiconductor region.Type: ApplicationFiled: April 1, 2013Publication date: March 12, 2015Inventors: Tadayoshi Miyamoto, Kazuatsu Ito, Mitsunobu Miyamoto, Yutaka Takamaru
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Publication number: 20150053969Abstract: This semiconductor device (100) includes: a gate electrode (3); a gate insulating layer (4); an oxide layer (50) which is formed on the gate insulating layer (4) and which includes a first conductor region (55) and a first semiconductor region (51) that overlaps at least partially with the gate electrode (3) with the gate insulating layer (4) interposed between them; a source electrode (6s) formed to contact with the upper surface of the first semiconductor region (51) of the oxide layer (50); a drain electrode (6d) which is formed to contact with the upper surface of the first semiconductor region (51) of the oxide layer (50) and which is electrically connected to the first conductor region (55); and a conductive layer (60) which is formed in contact with the upper surface of the oxide layer (50) and which a plurality of holes (66) or notches.Type: ApplicationFiled: March 29, 2013Publication date: February 26, 2015Inventors: Kazuatsu Ito, Yutaka Takamaru, Tadayoshi MIiyamoto, Mitsunobu Miyamoto, Makoto Nakazawa, Yasuyuki Ogawa, Seiichi Uchida, Shigeyasu Mori
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Publication number: 20150041800Abstract: This semiconductor device (100A) includes: a substrate (1); a gate electrode (3) and a first transparent electrode (2) which are formed on the substrate (1); a first insulating layer (4) formed over the gate electrode (3) and the first transparent electrode (2); an oxide semiconductor layer (5) formed on the first insulating layer (4); source and drain electrodes (6s, 6d) electrically connected to the oxide semiconductor layer (5); and a second transparent electrode (7) electrically connected to the drain electrode (6d). At least a portion of the first transparent electrode (2) overlaps with the second transparent electrode (7) with the first insulating layer (4) interposed between them, and the oxide semiconductor layer (5) and the second transparent electrode (7) are formed out of the same oxide film.Type: ApplicationFiled: January 24, 2013Publication date: February 12, 2015Inventors: Tadayoshi Miyamoto, Kazuatsu Ito, Shigeyasu Mori, Mitsunobu Miyamoto, Yasuyuki Ogawa, Makoto Nakazawa, Seiichi Uchida, Takuya Matsuo
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Publication number: 20140367677Abstract: This semiconductor device (100A) includes: a substrate (2); a gate electrode (3) formed on the substrate (2); a gate insulating layer (4) formed over the gate electrode (3); an oxide semiconductor layer (5) formed on the gate insulating layer (4); source and drain electrodes (6s, 6d) electrically connected to the oxide semiconductor layer (5); a first transparent electrode (7) electrically connected to the drain electrode (6d); an interlayer insulating layer (8) including a dielectric layer (8a) formed over the source and drain electrodes (6s, 6d); and a second transparent electrode (9) formed on the interlayer insulating layer (8). At least a portion of the second transparent electrode (9) overlaps with the first transparent electrode (7) with the dielectric layer (8a) interposed between them, and the oxide semiconductor layer (5) and the first transparent electrode (7) are formed out of the same oxide film.Type: ApplicationFiled: January 24, 2013Publication date: December 18, 2014Inventors: Tadayoshi Miyamoto, Kazuatsu Ito, Shigeyasu Mori, Mitsunobu Miyamoto, Yasuyuki Ogawa, Makoto Nakazawa, Takuya Matsuo, Seiichi Uchida
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Publication number: 20140361295Abstract: A semiconductor device (100A) includes a substrate (2), an oxide semiconductor layer (5) formed on the substrate (2), source and drain electrodes (6s, 6d) electrically connected to the oxide semiconductor layer (5), a first transparent electrode (7) electrically connected to the drain electrode (6d), a dielectric layer (8) formed on the source and drain electrodes (6s, 6d), and a second transparent electrode (9) formed on the dielectric layer (8). The upper and/or lower surface(s) of the first transparent electrode (7) contacts with a reducing insulating layer (8a) with the property of reducing an oxide semiconductor included in the oxide semiconductor layer (5). The second transparent electrode (9) overlaps at least partially with the first transparent electrode (7) via the dielectric layer (8). The oxide semiconductor layer (5) and the first transparent electrode (7) are formed out of the same oxide film.Type: ApplicationFiled: January 24, 2013Publication date: December 11, 2014Inventors: Tadayoshi Miyamoto, Kazuatsu Ito, Shigeyasu Mori, Mitsunobu Miyamoto, Yasuyuki Ogawa, Makoto Nakazawa, Seiichi Uchida, Takuya Matsuo
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Publication number: 20140125907Abstract: A TFT substrate (100) is provided with TFTs disposed on a substrate (2), first insulating layers (24, 26) disposed above the TFTs, a lower layer transparent electrode (12) disposed above the first insulating layers (24, 26), a second insulating layer (28) covering the lower layer transparent electrode (12), and pixel electrodes (10) disposed on the second insulating layer (28), in which an auxiliary capacitance (Cs) is formed by means of the lower layer transparent electrode (12), the second insulating layer (28), and the pixel electrode (10). The TFT and the pixel electrode (10) are electrically connected via a contact hole (34) penetrating the first insulating layers (24, 26) and the second insulating layer (28). A connecting transparent electrode (14) is disposed within the contact hole (34).Type: ApplicationFiled: June 15, 2012Publication date: May 8, 2014Applicant: SHARP KABUSHIKI KAISHAInventors: Makoto Nakazawa, Mitsunobu Miyamoto