Patents by Inventor Mitsunobu Miyamoto

Mitsunobu Miyamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130334528
    Abstract: A semiconductor device including a semiconductor layer, a plurality of electrode portions each overlapping the semiconductor layer, and an insulating film placed between the plurality of electrode portions to lie on the semiconductor layer is fabricated. The fabrication method includes the steps of: forming an oxide semiconductor layer part of which is covered with the insulating film; forming a conductive material layer to cover the oxide semiconductor layer and the insulating film; forming the plurality of electrode portions from the conductive material layer by photolithography and plasma dry etching, to expose part of the oxide semiconductor layer from the plurality of electrode portions and the insulating film; and removing the part of the oxide semiconductor layer exposed from the plurality of electrode portions and the insulating film to form the semiconductor layer.
    Type: Application
    Filed: February 22, 2012
    Publication date: December 19, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: Mitsunobu Miyamoto
  • Publication number: 20130187155
    Abstract: A method of manufacturing a thin film transistor substrate (1) includes at least the steps of: forming a gate electrode (15) on an insulating substrate (10) by using a first photomask; forming a channel protective film (21) on an oxide semiconductor layer (13) so as to cover a channel region (C) by using a second photomask; forming a source electrode (19) on the oxide semiconductor layer (13) by using a third photomask; and forming a planarizing film (18) on an interlayer insulating film (17) by using a fourth photomask.
    Type: Application
    Filed: October 11, 2011
    Publication date: July 25, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: Mitsunobu Miyamoto
  • Patent number: 8420458
    Abstract: A semiconductor device has a planarizing layer that is made of an inorganic film, and has a recessed portion formed in a region thereof in which a conductive film is disposed. A first contact hole penetrating through at least an interlayer insulating film is formed on a first wiring layer, while a second contact hole penetrating through at least the interlayer insulating film is formed on the conductive film so as to run through the inside of the recessed portion.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: April 16, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Makoto Nakazawa, Mitsunobu Miyamoto
  • Patent number: 8362623
    Abstract: A first contact hole that passes through a planarizing film layered on a first interlayer insulating film, a second interlayer insulating film that covers the surface of the planarizing film and the inner surface of the first contact hole, a third interlayer insulating film layered on the second interlayer insulating film, and a second contact hole formed with a small inner diameter inside the first contact hole and passing through the first to the third interlayer insulating films are formed. Over the third interlayer insulating film and inside the second contact hole, a second conductive film electrically connected to a first conductive film is formed.
    Type: Grant
    Filed: July 27, 2009
    Date of Patent: January 29, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Makoto Nakazawa, Mitsunobu Miyamoto
  • Publication number: 20120032263
    Abstract: A semiconductor device has a planarizing layer that is made of an inorganic film, and has a recessed portion formed in a region thereof in which a conductive film is disposed. A first contact hole penetrating through at least an interlayer insulating film is formed on a first wiring layer, while a second contact hole penetrating through at least the interlayer insulating film is formed on the conductive film so as to run through the inside of the recessed portion.
    Type: Application
    Filed: November 25, 2009
    Publication date: February 9, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Makoto Nakazawa, Mitsunobu Miyamoto
  • Publication number: 20110241219
    Abstract: A first contact hole that passes through a planarizing film layered on a first interlayer insulating film, a second interlayer insulating film that covers the surface of the planarizing film and the inner surface of the first contact hole, a third interlayer insulating film layered on the second interlayer insulating film, and a second contact hole formed with a small inner diameter inside the first contact hole and passing through the first to the third interlayer insulating films are formed. Over the third interlayer insulating film and inside the second contact hole, a second conductive film electrically connected to a first conductive film is formed.
    Type: Application
    Filed: July 27, 2009
    Publication date: October 6, 2011
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Makoto Nakazawa, Mitsunobu Miyamoto