Abstract: A visual image signal processing apparatus includes: an overlaying unit for overlaying a brightness reference signal at a predetermined position in a fly-back period of an input visual image signal; a first clamping unit for clamping an output from the overlaying unit at a predetermined clamping voltage; a detecting unit for applying an output from the first clamping unit to a driving electrode of a cathode ray tube and for detecting a beam current flowing based on the brightness reference signal overlaid in the input visual image signal; and a second clamping unit for controlling the predetermined clamp voltage based on the beam current detected by the detecting unit.

Abstract: A cathode ray tube control apparatus includes phosphor display screen, three electron guns for emitting R, G, B electron beams to the display screen, a shadow mask placed between the electron guns and the display screen, and index phosphors deposited on the shadow mask and having at least two line elements diagonal to a horizontal scanning direction of the electron beam for generating a signal according to the electron beam scan. Further provided are detector for detecting beam crossing points over the index phosphor, and correction circuit for correcting the deflection of the electron beam based on the detected beam crossing points.

Abstract: A refresh control circuit for a pseudo static random access memory includes a refresh control signal output circuit for outputting a refresh control signal to accomplish refresh control of the pseudo static random access memory, and includes a delay circuit. A first chip enable signal from a control device such as a MPU is delayed by the delay circuit and outputted as a second chip enable signal for the PSRAM. As the first chip enable signal level changes from a selection level to a non-selection level, the refresh control signal level changes to a non-refresh level. This state is maintained for a predetermined period. After the second chip enable signal changes from the selection level to the non-selection level, the refresh control signal returns from the non-refresh level to the refresh level. Thus, the PSRAM enters into the refresh state during the non-selection state, and is refreshed. This refresh operation is necessarily performed after an access to PSRAM.

Abstract: A subsample signal processing apparatus includes a wide-band D/A converter receiving a digital television signal which is compressed in band by subsampling. A signal processor subjects a video signal portion of an output signal from the D/A converter to wide-band processing. The signal processor subjects a sync signal portion of the output signal from the D/A converter to narrow-band processing. An output terminal of the signal processor and an input terminal of a subsequent A/D converter are coupled with wide-band coupling characteristics.

Abstract: A picture signal processing apparatus of a TV set, which has a picture signal memory/processing circuit to which picture signals are inputted. This picture signal memory/processing circuit includes a frame memory and has two alternative functions. One of the functions is to apply LPF processing in a temporal domain to a high frequency signal component, and the other function is to take out and output a still picture signal from the picture signal.

Abstract: A refresh control circuit for a pseudo static random access memory includes a refresh control signal output circuit for outputting a refresh control signal to accomplish refresh control of the pseudo static random access memory, and includes a delay circuit. A first chip enable signal from a control device such as a MPU is delayed by the delay circuit and outputted as a second chip enable signal for the PSRAM. As the first chip enable signal level changes from a selection level to a non-selection level, the refresh control signal level also changes to a non-refresh level. This state is maintained for a predetermined period. After the second chip enable signal changes from the selection level to the non-selection level, the refresh control signal returns from the non-refresh level to the refresh level. Thus, the PSRAM enters into the refresh state during the non-selection state, and is refreshed. This refresh operation is necessarily performed after an access to PSRAM.

Abstract: A semiconductor memory device has a memory cell matrix in which a plurality of memory cells are connected in rows by work lines and in columns by bit lines. The device comprises cell row groups each of which is formed by memory cell rows commonly activated by several row address signals at a first selection stage, a row group selection decoder having the smallest decoding circuits as a first stage decoder each connected to the row group(s) by first stage word line and commonly activating any group(s) at the first row selection stage by several row address signals, and a row selection decoder as a second stage decoder having the smallest decoding units entirely provided in the matrix and each activating any cell row(s) at a second selection stage by remaining row address signals.

Abstract: A television receiver is provided with two field memories for storing movement control signals, an OR circuit, a frame memory for storing the present and previous fields, a pair of switches controlled by a freeze signal, a switch controlled by the output signal of the OR circuit, and another switch for changing over its output signal to and from the output signal from the switch controlled by the OR circuit and the signal from the frame memory representing the present field. One frame's worth of video signals of the present field and the previous field are stored in the frame memory by a freeze signal. The signals stored in the frame memory provide a freeze picture having no multi-line dimness by virtue of using the present field and the previous field for the still picture image portion and the present field for the moving picture image portions of the present field and the previous field.

Abstract: A semiconductor memory having dynamic memory cells includes a determining circuit for determining whether or not it is necessary to refresh the dynamic memory cells, and only when it is necessary, outputting a refresh execution signal in response to a refresh request signal from an external circuit, and a circuit for executing a refresh operation in response to the refresh execution signal. Even if the refresh request signal is supplied, a refresh operation is not executed unless the determining circuit determines that the refresh operation is necessary, thus dispensing with unnecessary refresh operations. Preferably, the determining circuit includes a timer which outputs a signal at every predetermined period. Only when the signal is output from the timer, is the refresh request signal from an external circuit accepted and the refresh execution signal output.

Abstract: A clamp system for television signal comprises a first clamp device for clamping to a clamp control voltage supplied from an external source by a horizontal clamp pulse and a second clamp device for controlling the DC potential of the television signal by adding the externally-supplied control voltage to an input television signal. The first clamp device is used during the period requiring an early clamp start, and the second clamp device is operated under normal conditions.

Abstract: An image signal processing apparatus is provided which is applicable to a motion adaptive Y/C separation of an NTSC signal and a time-domain/spatial interpolation of a high definition television signal band-compressed by sub-Nyquist sub-sampling. The apparatus includes a still image processing circuit having frame memories, a motion image processing circuit having a line memory, a mixing circuit for mixing outputs of these processing circuits, a circuit for detecting image motion of an input image signal and applying a resultant control signal to the mixing circuit, and a signal mode control circuit for selectively adapting the image processing circuits for the processing of the NTSC signal or the high definition television signal.

Abstract: A main row decoder for driving main word lines in a main memory cell array includes partial decoders the number of which is equal to the number of the main word lines. Each partial decoder includes a NAND gate for receiving row address signals, an inverter for driving a corresponding main word line in response to an output from the NAND gate, a fuse element connected between the output terminal of the NAND gate and the input terminal of the inverter, and a MOS transistor connected between the input terminal of the inverter and a power supply voltage.

Abstract: During a data-clearing operation, while maintaining in the OFF state the transfer gate transistors in each of the static type memory cells associated with at least one column, the source of one of two drive transistors incorporated in the memory cell is set to a high potential level, and the source of the other drive transistor to a low level. As a result, the clearing operation is performed to a minimum of 1 column in the memory cell matrix. Due to the arrangement of the memory device, no address-selecting operation is required for selecting a memory cell during the clearing operation. Moreover, the clearing operation is carried out in a minimum unit of 1 column in the memory cell matrix. Consequently, the processing time for the clearing operation is reduced. Furthermore, the DC current flowing during the clearing operation is reduced, since the transfer gate transistor in the memory cell is maintained in the OFF state during the clearing operation, with the result that the power consumption is lowered.

Abstract: A television signal receiving apparatus of the type in which when performing a picture in picture operation by receiving a plurality of picture signals compressed in band width by multiple sub-Nyquist sampling, a sub-channel signal is first subjected to a spatial interpolating process and combined with a main-channel signal. The still picture portion and moving picture portion of a first input signal are restored to a field offset sub-sampled first picture signal, and a second input signal is restored to a field offset sub-sampled picture signal, subjected to a size-reducing process by time base compression in the vertical and horizontal directions of the picture and delivered as a second picture signal of the form synchronized in phase with a given position of the first picture signal. The first and second picture signals are time-division multiplexed to deliver a third picture signal onto a picture screen.

Abstract: Disclosed is an automatic gain control device which comprises: a first amplitude detection circuit for detecting an average amplitude value of a television video signal, a peak amplitude value of the same television video signal, or a value obtained by mixing the average amplitude value and the peak amplitude value with a predetermined mixing ratio; a second amplitude detection circuit for detecting an amplitude value of a vertical or horizontal synchronizing signal in the television video signal; an amplitude control circuit for controlling an amplitude of an input television video signal; a synchronization circuit for detecting a vertical synchronizing signal and a horizontal synchronizing signal in the television video signal so as to generate various pulses including a clock pulse synchronized with the input television video signal by controlling an oscillation frequency of an oscillation circuit; and a synchronization phase lock detection circuit for detecting whether the synchronization circuit has been

Abstract: A control signal output circuit for outputting a control signal in response to first and second input signals and a power source voltage, comprises an inverter which inverts one of the first and second input signals and outputs an inverted signal. The control signal output circuit further comprises a logic circuit which outputs a control signal in response to the inverted signal and the other of the first and second input signals. A switch is further provided to disconnect the inverter from the power source voltage in response to the other of the first and second input signals.

Abstract: A virtual type static semiconductor memory device according to the present invention comprises a refresh detector circuit for detecting the enabling operation of a refresh control circuit and a terminal for outputting to an outside a detection signal which is generated from the refresh detector circuit. The virtual type static semiconductor memory device informs a present refresh operation to the outside when it is accessed from the outside during the time period in which a refresh operation is conducted in the semiconductor memory device. A system employing the semiconductor memory device allows a slow access at that time only and allows access to be gained to the semiconductor memory device at high speed at other times.

Abstract: An output circuit for outputting an output signal in response to an input signal having first and second voltage levels, comprises first circuit responsive to the input signal for generating a first signal including a low impedance portion corresponding to the duration of the second level of the input signal. A second circuit responsive to the input signal is further provided to supply a second signal including a low impedance portion which exists after the duration of the second voltage level of the input signal. The first and the second signals are combined to produce the output signal.

Abstract: A static semiconductor memory comprises a word line, a memory cell array divided into a plurality of blocks in an extending direction of the word line, each block including a plurality of sections each of which includes a plurality of static memory cells, a controller, a section data line provided for each section, first sense amplifiers, a block data line provided for each block, second sense amplifiers, a main data line and a latch circuit for latching data on the main data line. The controller selects an arbitrary section in the memory cell array at the time of data readout and controls the reading of data from memory cells included in the selected section. The section data line is supplied with data read out from the memory cells. The first sense amplifiers, coupled at their input terminals to the section data line, are activated only when their associated section is selected. The individual first sense amplifiers in the same block have their output terminals commonly coupled to the block data line.

Abstract: When the receiving system for a band-compression image signal receives a dropout signal representing a dropout portion of an image signal, an output of the third delay circuit of the temporal filter for motion detection processing, that is, motion information of an image signal, which precedes by one field, and a dropout signal activate the signal selection control circuit to produce an output signal for controlling the operation of the signal selection circuit, so that an output signal of the first delay circuit is selected for a static portion of an image, and an output signal of the dropout compensation circuit is selected for a moving portion of an image, so as to effect compensation control of the dropout portion of an image signal, thereby preventing deterioration of the quality of an image.