Patents by Inventor Mitsuo Isobe
Mitsuo Isobe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 4882708Abstract: A precharge circuit is provided between bit lines, on the one hand, and a power source potential on the other. The precharge circuit is controlled to be conductive/nonconductive by a clear signal. A control unit is also provided, which controls a decoder when the clear signal is supplied so as to set all the word lines in a selective state. In a clear mode, writing circuits write the same data simultaneously into all of the memory cells.Type: GrantFiled: January 19, 1988Date of Patent: November 21, 1989Assignee: Kabushiki Kaisha ToshibaInventors: Shigeyuki Hayakawa, Mitsuo Isobe, Takayuki Ohtani
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Patent number: 4879686Abstract: A semiconductor memory device comprising a memory cell-selecting section, an input supply control section, and a bit-line potential control section. The memory cell-selecting section includes a row decoder and a first gate circuit coupled to the output thereof. The memory cell-selecting section drives all the memory cells making up the memory device, when it is set in the mode for clearing the memory device, and the input data supply control section disconnects a pair of bit lines from a write circuit when the control section is set in this same mode. When the bit-line potential control section is set in the memory-clearing mode, it sets the potential of one of the bit lines at a high level, and the potential of the other bit line at a low potential.Type: GrantFiled: March 3, 1988Date of Patent: November 7, 1989Assignee: Kabushiki Kaisha ToshibaInventors: Azuma Suzuki, Takayuki Ootani, Mitsuo Isobe
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Patent number: 4858197Abstract: In an output buffer control circuit of a memory, the set/reset state of a flip-flop is controlled by an address transition detection output and a read detection output supplied when completion of data read from a memory cell is detected, and the active/inactive state of an output buffer for outputting the readout data from the memory cell is controlled by an output from the flip-flop. According to this arrangement, when an address input transits and the address transition detection output is enabled, the output buffer is inactivated. When data is read out from the memory cell and the read detection output is enabled after the address input transits, the output buffer can be activated.Type: GrantFiled: May 24, 1988Date of Patent: August 15, 1989Assignee: Kabushiki Kaisha ToshibaInventors: Akira Aono, Mitsuo Isobe
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Patent number: 4833652Abstract: A defect detection circuit for detecting a defect of a memory cell, a counter for counting defects detected by the defect detect circuit, and a remediableness determination unit for determining whether a count of the counter allows remedy by a redundancy circuit, are provided in a tester for a semiconductor memory or on a memory chip having a redundancy circuit. When the count of the counter is the same as or smaller than the number of at least one of the auxiliary rows and columns of the redundancy circuit, the memory is determined to be "remediable." Otherwise, the memory is determined to be "unremediable." When the count of the counter exceeds the number of at least one of the auxiliary rows and columns of the redundancy circuit, the memory test is interrupted.Type: GrantFiled: March 22, 1988Date of Patent: May 23, 1989Assignee: Kabushiki Kaisha ToshibaInventors: Mitsuo Isobe, Tohru Kimura
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Patent number: 4813022Abstract: The threshold voltage of bit line percharge/equalize MOS transistors is smaller than that of normally ON type bit line pull-up transistors. With this feature, there is no current flows through a bit line from power source V.sub.DD during a read-out operation. The voltage difference between a pair of bit lines can be increased at high speed, thereby increasing the read-out speed.Type: GrantFiled: December 22, 1987Date of Patent: March 14, 1989Assignee: Kabushiki Kaisha ToshibaInventors: Masataka Matsui, Tetsuya Iizuka, Jun-ichi Tsujimoto, Takayuki Ohtani, Mitsuo Isobe
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Patent number: 4744063Abstract: A static memory has an address transition detector, an input data transition detector and a pulse signal generator. When a detector detects that an input address or input data has changed, the pulse signal generator produces a pulse signal having a width longer than the shorter of the data-reading or data-writing cycle. This pulse signal controls the period of time during which a penetrating DC current flows between two power sources via some of the components of the memory.Type: GrantFiled: May 24, 1984Date of Patent: May 10, 1988Assignee: Kabushiki Kaisha ToshibaInventors: Takayuki Ohtani, Takayasu Sakurai, Mitsuo Isobe, Tetsuya Iizuka
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Patent number: 4697112Abstract: There is disclosed a sense amplifier characterized by comprising a pull-up circuit. The pull-up circuit comprises a first transistor arranged between the first of a pair of output nodes and a pull-up power source potential node, and a second transistor arranged between the second of the pair of output nodes and the pull-up power source potential node. The gate of the first transistor is connected to the second output node and the gate of the second transistor is connected to the first output node.Type: GrantFiled: June 25, 1986Date of Patent: September 29, 1987Assignee: Kabushiki Kaisha ToshibaInventors: Takayuki Ohtani, Mitsuo Isobe, Akira Aono, Nobuaki Urakawa
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Patent number: 4592026Abstract: In a memory device, a plurality of memory cells are connected to bit line pairs. A precharge circuit is controlled by a chip enable signal during a stand-by state and by an address transition detector signal during an active state, to charge the bit line pairs up to a given power source voltage.Type: GrantFiled: December 23, 1983Date of Patent: May 27, 1986Assignee: Shaibaura Denki Kabushiki KaishaInventors: Naohiro Matsukawa, Mitsuo Isobe, Takayasu Sakurai
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Patent number: 4587638Abstract: In the semiconductor memory device according to the present invention, when there is a defective portion in the memory cells, those memory cells are replaced by redundant memory cells. When defective portions are discovered in the memory cells, the fuse elements corresponding to the memory cells having the defective portions are cut off. Voltages of the select lines connected to the memory cells having the defective portions are held at an L level by the resistors. Due to this, the memory cells having the defective portions are not selected.Type: GrantFiled: July 12, 1984Date of Patent: May 6, 1986Assignee: Micro-Computer Engineering CorporationInventors: Mitsuo Isobe, Takayasu Sakurai, Kazuhiro Sawada, Tetsuya Iizuka, Takayuki Ohtani, Akira Aono
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Patent number: 4563593Abstract: A transition detector circuit comprises a first invertor train comprising 2n stages of invertors (n: positive integer including zero), the input thereof being connected to a signal input terminal while the output thereof is connected to an in-phase output terminal, a second invertor train comprising 2n+1 stages of invertors, the input thereof being connected to the signal input terminal, while the output thereof is connected to an antiphase output terminal, a third invertor train comprising at least one stage of an invertor, which is connected to the output of the first invertor train, a fourth invertor train, comprising at least one stage of an invertor, which is connected to the output of the second invertor train, and a fifth invertor train comprising at least one stage of an invertor, which is connected to the signal input terminal.Type: GrantFiled: October 3, 1983Date of Patent: January 7, 1986Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Mitsuo Isobe, Takayuki Ohtani
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Patent number: 4524389Abstract: In a synchronous video detector circuit using a phase-locked loop, the synchronous detection of a video IF signal is effected with a synchronous carrier signal reproduced by the PLL including a voltage-controlled oscillator. Each of a phase comparator of the PLL and a synchronous video detector has its input terminal connected to an output terminal of a video IF amplifier by untuned coupling, and arranged on the output side of the synchronous video detector is a phase-locked mode detector for detecting that the PLL is in its phase-locked mode. The phase-locked mode detector is adapted to control the band width of a low-pass filter of the PLL in either a narrow band mode or a wide band mode and the low-pass filter is controlled to operate in the narrow band mode only when the PLL is in the phase-locked mode of operation.Type: GrantFiled: November 2, 1982Date of Patent: June 18, 1985Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Mitsuo Isobe, Tetsuo Kutsuki, Namio Yamaguchi, Toshihide Tanaka
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Patent number: 4146843Abstract: An RF-IF signal receiving circuit of a television receiver controls a tuner which receives an amplitude modulated RF signal and converts it to an IF signal and an IF signal carrier generator for demodulating the amplitude modulated signal from the IF signal by synchronous detection, using a phase synchronous loop. A sweep voltage generator of a voltage-controlled oscillator in the phase synchronous loop comprises an envelope detector which is DC-coupled to an output of an amplitude synchronous detector and a low pass filter in order to enhance the pull-in range of the phase synchronous loop.Type: GrantFiled: November 1, 1977Date of Patent: March 27, 1979Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Mitsuo Isobe
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Patent number: 4010401Abstract: A constant voltage converter for use with a cathode ray tube in which a voltage regulator is controlled by both the output of the regulator and beam current from the cathode ray tube by way of beam detecting means. The output of the regulator is applied separately to a stabilizing circuit including another feedback circuit for CRT, and also to deflection circuits so as to better prevent fluctuation of picture on the CRT.Type: GrantFiled: December 6, 1973Date of Patent: March 1, 1977Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Noboru Yasumatsuya, Mitsuo Isobe
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Patent number: 3953884Abstract: A video amplifier is disclosed wherein the luminance signal is applied to the collector circuit of a differential amplifier comprising two transistors, the color difference signal is applied to the base of one of the two transistors, and the primary color signal is derived across a load resistor coupled to the collector circuit.Type: GrantFiled: October 15, 1974Date of Patent: April 27, 1976Inventors: Mitsuo Isobe, Toshihiko Yoshino