Abstract: In forming an ohmic electrode on a back surface of an n-type SiC substrate, an n+-type semiconductor region is formed in a surface layer of the back surface of an n-type epitaxial substrate by ion implantation. In this ion implantation, the impurity concentration of the n+-type semiconductor region is a predetermined range and preferably a predetermined value or less, and an n-type impurity is implanted by acceleration energy of a predetermined range such that the n+-type semiconductor region has a predetermined thickness or less. Thereafter, a nickel layer and a titanium layer are sequentially formed on the surface of the n+-type semiconductor region, the nickel layer is heat treated to form a silicide, and the ohmic electrode formed from nickel silicide is formed. In this manner, a back surface electrode that has favorable properties can be formed while peeling of the back surface electrode can be suppressed.

Abstract: An infrared ray absorbing film is selectively formed on a surface of a silicon carbide semiconductor substrate in a predetermined area. An aluminum film and a nickel film are sequentially formed in this order on the silicon carbide semiconductor substrate in an area excluding the predetermined area in which the infrared ray absorbing film is formed. The silicon carbide semiconductor substrate is thereafter heated using a rapid annealing process with a predetermined heating rate to form an electrode. The rapid annealing process converts the nickel film into a silicide and, with the aluminum film, provides an electrode having ohmic contact.

Abstract: On a silicon carbide semiconductor substrate, heat treatment is performed after one layer or two or more layers of an oxide film, a nitride film, or an oxynitride film are formed as a gate insulating film. The heat treatment after the gate insulating film is formed is performed for a given period in an atmosphere that includes H2 and H2O without including O2. As a result, hydrogen or hydroxyl groups can be segregated in a limited region that includes the interface of the silicon carbide substrate and the gate insulating film. The width of the region to which the hydrogen or hydroxyl groups is segregated is from 0.5 nm to 10 nm. In such a manner, the interface state density can be lowered and high channel mobility can be realized.

Abstract: In producing a MOS silicon carbide semiconductor device, after a first heat treatment (oxynitride) is performed in an oxidation atmosphere including nitrous oxide or nitric oxide, a second heat treatment including hydrogen is performed, whereby in the front surface of a SiC epitaxial substrate, a gate insulating film is formed. A gate electrode is formed and after an interlayer insulating film is formed, a third heat treatment is performed to bake the interlayer insulating film. After contact metal formation, a fourth heat treatment is performed to form a reactive layer of contact metal and the silicon carbide semiconductor. The third and fourth heat treatments are performed in an inert gas atmosphere of nitrogen, helium, argon, etc., and a manufacturing method of a silicon carbide semiconductor device is provided achieving a normally OFF characteristic and lowered interface state density.

Abstract: A silicon carbide vertical MOSFET having low ON-resistance and high blocking voltage. A first deposition film of low concentration silicon carbide of a first conductivity type is formed on the surface of a high concentration silicon carbide substrate of a first conductivity type. Formed on the first deposition film is a second deposition film that includes a high concentration gate region of a second conductivity type, with a first region removed selectively. A third deposition film is formed on the second deposition film, which includes a second region that is wider than the selectively removed first region, a high concentration source region of a first conductivity type, and a low concentration gate region of a second conductivity type. A low concentration base region of a first conductivity type is formed in contact with the first deposition film in the first and second regions.

Abstract: A SiC MISFET, in which a source region and a drain region (3, 4) are formed in a one-conductivity-type SiC semiconductor region (2), in which a recess (5) with a predetermined depth is formed in a portion of the SiC semiconductor region sandwiched between the source and drain regions, with the recess having two side faces in contact with the source and drain regions, and a bottom face connecting the two side faces, and in which portions (3a, 4a) of the source and drain regions adjacent to the vicinity of both ends of the bottom face of the recess are thinner than other portions.

Abstract: A silicon carbide vertical MOSFET having low ON-resistance and high blocking voltage is provided. For this, a first deposition film (2) of low concentration silicon carbide of a first conductivity type is formed on the surface of a high concentration silicon carbide substrate (1) of a first conductivity type. Formed on the first deposition film (2) is a second deposition film (31) that comprises a high concentration gate region of a second conductivity type, with a first region removed selectively. A third deposition film (32) formed on the second deposition film, which comprises a second region that is wider than the selectively removed first region, a high concentration source region (5) of a first conductivity type and a low concentration gate region (11) of a second conductivity type. A low concentration base region (4) of a first conductivity type is formed in contact with the first deposition film (2) in the first and second regions.

Abstract: A SiC MISFET, in which a source region and a drain region (3, 4) are formed in a one-conductivity-type SiC semiconductor region (2), in which a recess (5) with a predetermined depth is formed in a portion of the SiC semiconductor region sandwiched between the source and drain regions, with the recess having two side faces in contact with the source and drain regions, and a bottom face connecting the two side faces, and in which portions (3a, 4a) of the source and drain regions adjacent to the vicinity of both ends of the bottom face of the recess are thinner than other portions.

Abstract: This invention has a cell incorporating a built-in Schottky diode region disposed in at least part of an elementary cell that constitutes an SiC vertical MOSFET provided in a low-density p-type deposit film with a channel region and a base region inverted to an n-type by ion implantation. This built-in Schottky diode region has built therein a Schottky diode of low on-resistance that is formed of a second deficient pan disposed in a high-density gate layer, a second n-type base layer penetrating a low-density p-type deposit layer formed thereon, reaching an n-type drift layer of the second deficient part and attaining its own formation in consequence of inversion of the p-type deposit layer into an n-type by the ion implantation of an n-type impurity from the surface, and a source electrode connected in the manner of forming a Schottky barrier to the surface-exposed part of the second n-type base layer.

Abstract: A semiconductor device and a method of manufacturing the device using a (000-1)-faced silicon carbide substrate are provided. A SiC semiconductor device having a high blocking voltage and high channel mobility is manufactured by optimizing the heat-treatment method used following the gate oxidation. The method of manufacturing a semiconductor device includes the steps of forming a gate insulation layer on a semiconductor region formed of silicon carbide having a (000-1) face orientation, forming a gate electrode on the gate insulation layer, forming an electrode on the semiconductor region, cleaning the semiconductor region surface. The gate insulation layer is formed in an atmosphere containing 1% or more H2O (water) vapor at a temperature of from 800° C. to 1150° C. to reduce the interface trap density of the interface between the gate insulation layer and the semiconductor region.

Abstract: In an SiC vertical MOSFET comprising a channel region and an n-type inverted electron guide path formed through ion implantation in a low-concentration p-type deposition film, the width of the channel region may be partly narrowed owing to implantation mask positioning failure, and the withstand voltage of the device may lower, and therefore, the device could hardly satisfy both low on-resistance and high withstand voltage. In the invention, second inverted layers (41, 42) are provided at the same distance on the right and left sides from the inverted layer (40) to be the electron guide path in the device, and the inverted layers are formed through simultaneous ion implantation using the same mask, and accordingly, the length of all the channel regions in the device is made uniform, thereby solving the problem.

Abstract: In an SiC vertical MOSFET comprising a channel region and an n-type inverted electron guide path formed through ion implantation in a low-concentration p-type deposition film, the width of the channel region may be partly narrowed owing to implantation mask positioning failure, and the withstand voltage of the device may lower, and therefore, the device could hardly satisfy both low on-resistance and high withstand voltage. In the invention, second inverted layers (41, 42) are provided at the same distance on the right and left sides from the inverted layer (40) to be the electron guide path in the device, and the inverted layers are formed through simultaneous ion implantation using the same mask, and accordingly, the length of all the channel regions in the device is made uniform, thereby solving the problem.

Abstract: This invention has a cell incorporating a built-in Schottky diode region disposed in at least part of an elementary cell that constitutes an SiC vertical MOSFET provided in a low-density p-type deposit film with a channel region and a base region inverted to an n-type by ion implantation. This built-in Schottky diode region has built therein a Schottky diode of low on-resistance that is formed of a second deficient pan disposed in a high-density gate layer, a second n-type base layer penetrating a low-density p-type deposit layer formed thereon, reaching an n-type drift layer of the second deficient part and attaining its own formation in consequence of inversion of the p-type deposit layer into an n-type by the ion implantation of an n-type impurity from the surface, and a source electrode connected in the manner of forming a Schottky barrier to the surface-exposed part of the second n-type base layer.

Abstract: In the SiC vertical MOSFET having a low-concentration p-type deposition film provided therein with a channel region and a base region resulting from reverse-implantation to n-type through ion implantation, dielectric breakdown of gate oxide film used to occur at the time of off, thereby preventing a further blocking voltage enhancement. This problem has been resolved by interposing of a low-concentration n-type deposition film between a low-concentration p-type deposition film and a high-concentration gate layer and selectively forming of a base region resulting from reverse-implantation to n-type through ion implantation in the low-concentration p-type deposition film so that the thickness of deposition film between the high-concentration gate layer and each of channel region and gate oxide layer is increased.

Abstract: Regarding output suppression control of a plurality of dispersed power sources linked to a high-voltage-to-low-voltage transformer of a commercial power system, the partiality of the output suppression of a plurality of dispersed power sources is eliminated and, cost increase of the dispersed power sources is prevented. If a voltage at a power receiving point of a dispersed power source 1a exceeds the upper limit of a proper value, then a power conditioner 4 suppresses an output to a power receiving point to store a surplus power into a storage battery 8 and transmit an output suppression start signal to a management unit 9. The management unit 9 transmits an output suppression command signal to the other dispersed power sources 1b through 1e of which the voltage at the power receiving point is not exceeding the upper limit of the proper value to make the other dispersed power sources 1b through 1e to suppress their outputs and store surplus power into storage batteries 8.

Abstract: A semiconductor device and a method of manufacturing the device using a (000-1)-faced silicon carbide substrate are provided. A SiC semiconductor device having a high blocking voltage and high channel mobility is manufactured by optimizing the heat-treatment method used following the gate oxidation. The method of manufacturing a semiconductor device includes the steps of forming a gate insulation layer on a semiconductor region formed of silicon carbide having a (000-1) face orientation, forming a gate electrode on the gate insulation layer, forming an electrode on the semiconductor region, cleaning the semiconductor region surface. The gate insulation layer is formed in an atmosphere containing 1% or more H2O (water) vapor at a temperature of from 800° C. to 1150° C. to reduce the interface trap density of the interface between the gate insulation layer and the semiconductor region.

Abstract: Regarding output suppression control of a plurality of dispersed power sources linked to a high-voltage-to-low-voltage transformer of a commercial power system, the partiality of the output suppression of a plurality of dispersed power sources is eliminated and, cost increase of the dispersed power sources is prevented. If a voltage at a power receiving point of a dispersed power source 1a exceeds the upper limit of a proper value, then a power conditioner 4 suppresses an output to a power receiving point to store a surplus power into a storage battery 8 and transmit an output suppression start signal to a management unit 9. The management unit 9 transmits an output suppression command signal to the other dispersed power sources 1b through 1e of which the voltage at the power receiving point is not exceeding the upper limit of the proper value to make the other dispersed power sources 1b through 1e to suppress their outputs and store surplus power into storage batteries 8.

Abstract: Regarding output suppression control of a plurality of dispersed power sources linked to a high-voltage-to-low-voltage transformer of a commercial power system, the partiality of the output suppression of a plurality of dispersed power sources is eliminated and, cost increase of the dispersed power sources is prevented. If a voltage at a power receiving point of a dispersed power source 1a exceeds the upper limit of a proper value, then a power conditioner 4 suppresses an output to a power receiving point to store a surplus power into a storage battery 8 and transmit an output suppression start signal to a management unit 9. The management unit 9 transmits an output suppression command signal to the other dispersed power sources 1b through 1e of which the voltage at the power receiving point is not exceeding the upper limit of the proper value to make the other dispersed power sources 1b through 1e to suppress their outputs and store surplus power into storage batteries 8.

Abstract: A method of manufacturing a semiconductor device that provides a semiconductor device having improved channel mobility includes a process of forming a gate insulation film of silicon oxide film, silicon nitride film or silicon oxide nitride film or the like on a silicon oxide substrate, and following formation of the gate insulation film on the silicon oxide substrate with heat treatment for a given time at a temperature range of 900° C. to 1000° C. in an atmosphere containing not less than 25% H2O (water).

Abstract: A silicon carbide vertical MOSFET having low ON-resistance and high blocking voltage. A first deposition film of low concentration silicon carbide of a first conductivity type is formed on the surface of a high concentration silicon carbide substrate of a first conductivity type. Formed on the first deposition film is a second deposition film that includes a high concentration gate region of a second conductivity type, with a first region removed selectively. A third deposition film is formed on the second deposition film, which includes a second region that is wider than the selectively removed first region, a high concentration source region of a first conductivity type, and a low concentration gate region of a second conductivity type. A low concentration base region of a first conductivity type is formed in contact with the first deposition film in the first and second regions.