Abstract: A condenser, a coil and a thin-thickness integrated circuit are placed between an upper cover sheet and a lower cover sheet, and adhesive is filled into the space between them, whereby a card is fabricated. Because the condenser, the coil and the thin-thickness integrated circuit are extremely thin, the resulting semiconductor device is highly resistant to bending and highly reliable at a low cost.

Abstract: Prevention of reduction in the production yield due to the increase in the area of a semiconductor chip permits a sophisticated-performance single-chip semiconductor device to be fabricated. This also permits a many-kind small-amount production of semiconductor devices to be implemented. After plural semiconductor chips 2 and 3 are fabricated separately, only defect-free chips of them are selected. The selected defect-free chips are connected in contact between their side walls of their densest faces of atoms of their substrates so that the surfaces 4a and 4b where elements are to be formed are located in the same plane. Thus, even when the chip area is increased, reduction of the production yield can be prevented, thereby permitting a large-area sophisticated-performance single chip semiconductor device to be fabricated.

Abstract: A semiconductor chip (105') and a substrate (102) are bonded with an organic adhesive layer (409) containing conductive particles (406), and a pad (405) and an electrode (412) are mutually, electrically connected through the conductive particles (406).The semiconductor chip (105') is formed by contacting a semiconductor wafer (105) attached to a tape (107) with an etchant while rotating the semiconductor wafer (105) within an in-plane direction at a high speed or reciprocating the wafer (105) laterally to uniformly etch the semiconductor wafer (105) thereby reducing the thickness thereof, and dicing the thus reduced wafer. The resultant thin chip (105') is hot-pressed by means of a heating head (106) for bonding on the substrate (102).In this way, a thin semiconductor chip can be formed stably at low costs and bonded on a substrate without causing any crack of the chip, thereby obtaining a semiconductor device which is unlikely to break owing to the bending stress from outside.

Abstract: A structure for connecting an integrated circuit chip to a wiring substrate which implements high-density packaging, high-density connection, high-speed signal transmission, and low cost. An integrated circuit is connected to a wiring substrate by means of flip-chip die bonding using an adhesive film. A direct through-hole connection is formed directly below a connecting pad so as to pass through the adhesive film and the wiring substrate. This direct through-hole connection directly connects the connecting pad to the wire. As a result of reduced area and thickness of the chip, the chip is mounted in high density, and high-density inputs and outputs are implemented by means of minute two-dimensional connections. Short wire connections directly connected to the chip permit high speed signal transmission, and high reliability is ensured by the dispersion of stress. Low-cost packaging can be effected by simple processes and facilities.

Abstract: A thin-film semiconductor device comprising at least a semiconductor element and a wiring is disclosed. A thin film of a protective insulating material is formed on the lower surface of the semiconductor element, and a substrate is bonded on the lower surface of the thin film. A method for fabricating the thin-film semiconductor device is also disclosed, in which a thin-film semiconductor circuit is formed on a silicon-on-insulator wafer, the silicon substrate on the reverse side of the silicon-on-insulator wafer is etched off, a thin-film semiconductor chip is formed and attached to the substrate, and the thin-film semiconductor chip and the substrate are wired to each other by printing.

Abstract: Integrated circuit devices, chips and methods of making and operating them are disclosed. The devices are specially adapted for high frequency operation e.g. at or above 1 GHz. Inductive noise caused by switching at these frequencies--and which can interfere with switching--is inhibited by using a large bypass capacitor connected between power and ground connections outside the chip, and a small bypass capacitor connected between the same power and ground connections but formed inside the chip. The smaller capacitor cuts noise attributable to the wiring between the larger capacitor and the chip. The chip can have many of the smaller capacitors, even one or more per gate. In the preferred embodiments, the small capacitors from power and ground bonding pads are formed at the front surface of the chip substrate. Tantalum pentoxide, and other suitable dielectrics having relative dielectric constant of 10 or more at 1 GHz, are used to form the capacitors.

Abstract: A flight velocity detection system using a truncated pyramid-shape multi-e Pitot probe in which an extreme end portion has a truncated pyramid-shape, a cylindrical hole is provided at the apex thereof, a total pressure tube of a smaller diameter than that of the cylindrical hole is secured at a position by a predetermined length determined by a relationship with the diameter of the cylindrical hole from the extreme end of the cylindrical hole, and groups of pressure holes comprised of a plurality of pressure holes are arranged in each of the truncated pyramid surfaces of the truncated pyramid shape. Items of pressure information detected by the probe are input into a velocity vector processor to convert them into electric signals, and signals are processed using pressure coefficients of the holes of the probe with respect to the velocity vector stored in advance in the velocity vector processor to calculate flight velocity vector (V, .alpha., .beta.

Abstract: A method for manufacturing a semiconductor integrated circuit device is described. The method comprises forming a plurality of macrocells each comprising a semiconductor integrated circuit on a semiconductor layer of an SOI (silicon on insulator) substrate, subjecting an insulating film for element separation and an insulating film in the substrate to wet etching thereby removing an unnecessary macrocell, and attaching a desired macrocell separated fabricated to the removed macrocell region. The semiconductor integrated circuit device is also described, which is free of defects and has multifunction and high reliability.

Abstract: In accordance with one aspect of the invention, a semiconductor integrated circuit is provided wherein an input circuit is formed by a phase split circuit having a bipolar transistor which outputs an inverted output from the collector and a non-inverted output from the emitter. The emitter follower output circuit is driven by an inverted output of the phase split circuit. Meanwhile, an emitter load of the emitter follower output circuit is formed by a transistor, and the emitter load transistor is temporarily driven conductively by a charging current of the capacitance to be charged by the rising edge of the non-inverted output of the phase split circuit. As a second aspect of the invention, a logic circuit is formed of a logic portion and an output portion. The output portion includes an emitter follower output transistor receiving an output signal generated by the logic portion and an active pull-down transistor receiving at its base a signal supplied thereto through a capacitance element.

Abstract: Herein disclosed is a logic circuit which has an input bipolar transistor for receiving an input signal at its base; variable impedance circuit having at least a first P-channel MOSFET connected between a first supply voltage and the collector of the input bipolar transistor; a second N-channel MOSFET connected between the emitter of the input bipolar transistor and a second supply voltage; an output bipolar transistor connected between the first supply voltage and the output terminal of the circuit for receiving the collector potential of the input bipolar transistor at its base; and a third, pull-down MOSFET connected between the output terminal and the second or third supply voltage.

Abstract: In accordance with one aspect of the invention, a semiconductor integrated circuit is provided wherein an input circuit is formed by a phase split circuit having a bipolar transistor which outputs an inverted output from the collector and a non-inverted output from the emitter. The emitter follower output circuit is driven by an inverted output of the phase split circuit. Meanwhile, an emitter load of the emitter follower output circuit is formed by a transistor, and the emitter load transistor is temporarily driven conductively by a charging current of the capacitance to be charged by the rising edge of the non-inverted output of the phase split circuit. As a second aspect of the invention, a logic circuit is formed of a logic portion and an output portion. The output portion includes an emitter follower output transistor receiving an output signal generated by the logic portion and an active pull-down transistor receiving at its base a signal supplied thereto through a capacitance element.

Abstract: A logic circuit comprising a phase divider circuit, a transistor receiving an inverted output from the phase divider circuit, and an active pull-down circuit coupled with an output terminal in connection with the transistor and adapted to be operated by a noninverted output from the phase divider circuit, in which the phase divider circuit is provided with a variable impedance circuit, which is coupled with the inverted output and of which the impedance is adapted to be varied according to the input signal.

Abstract: A semiconductor integrated circuit device has, in one embodiment, a pair of signal transmission lines formed over and insulated from a semiconductor substrate, a first circuit formed in the semiconductor substrate and electrically connected with one end of the pair of signal transmission lines for sending an electric signal, and a second circuit formed in the semiconductor substrate and electrically connected with the other end of the pair of signal transmission lines for receiving the electric signal propagating over the transmission line pair. A control resistance is electrically connected between the pair of transmission lines at the above-mentioned other end for controlling a delay time of the signal propagating over the pair of signal transmission lines between the opposite ends of the pair of signal transmission lines.

Abstract: The present invention relates to a logic correction for a random logic IC of a high integration density, and more particularly to an on-chip logic correction method wherein the upper surface of a chip is divided into a large number of macrocells, testing of the macrocells is made and each defective macrocell is corrected by replacement. Testing is performed after a primary wiring process that connects semiconductor elements into macrocells but before a secondary wiring process interconnecting the macrocells. After the testing, defective macrocells are replaced, and thereafter the secondary wiring process is performed. Testing is performed using testing pads in each macrocell, connected to the main circuit portion of the macrocell through shift register circuit portions. The macrocells are arranged in a lattice pattern. Wirings formed in the secondary wiring process have a larger cross-sectional area than wirings formed in the primary wiring process.

Abstract: A SPL (or Super Push-pull Logic) circuit is provided which includes: a first variable resistor circuit connected between the collector of an input transistor and a first supply voltage terminal (GND) a second variable resistor circuit connected between the emitter of the input transistor and a second supply voltage terminal (V.sub.EE) and a push-pull output circuit. The second variable resistor circuit includes an N-channel MOSFET which has its gate electrode made receptive of any of the output signals of the SPL circuit, a differentiated signal of the output signal, and an inverted signal of the input signal.

Abstract: A unitary semiconductor integrated circuit is constructed using a non-threshold logic NTL circuit for a circuit which has a light load or a light load driving capability, using an NTL circuit additionally provided with an emitter-follower output circuit for effecting a circuit having a comparatively heavy load, and using a super pull-down logic (SPL) circuit for effecting a circuit having a heavy load. The NTL circuit thereof which receives an output signal generated by the emitter-follower output circuit or from the SPL circuit associated with a preceding logic gate circuit stage uses, as its operating voltage, the operating voltage of the emitter-follower output circuit or that of the SPL circuit.

Abstract: Attempts have been made to increase the number of pins of packages accompanying the trend toward fabricating integrated circuits highly densely and in smaller sizes. The present invention provides technology for improving reliability in fabricating packages of the surface-mounted type that have increased number of pins. That is, when the packages are mounted on the wiring substrate, the lead pins that receive load from the axial direction exhibit bending strength which is smaller than the junction strength of solder at the junction portions. To achieve this object, the lead pins are made of a material having large resiliency such as a fiber-reinforced material, a transformation pseudo elastic material, an ultra-high tension material, or a heat-resistant ultra-high tension material.

Abstract: A semiconductor integrated circuit wherein an input circuit is formed by a phase split circuit consisting of a bipolar transistor which outputs an inverted output from the collector and non-inverted output from the emitter, the emitter follower output circuit is driven by an inverted output of the phase split circuit, meanwhile, an emitter load of the emitter follower output circuit is formed by a transistor, and the emitter load transistor is temporarily driven conductively by a charging current of the capacitance to be charged by the rising edge of the non-inverted output of the phase split circuit.

Abstract: An improved flip-flop circuit is provided which prevents the occurrence of soft errors due to .alpha. rays and the like emitted from a trace amount of radioactive materials contained in a semiconductor package material. The flip-flop circuit has a first logic circuit which holds data and produces a first logic signal and a second logic circuit which produces a second logic signal. A logic gate receives the first and second logic signals that are produced from the first and second logic circuits and which have the same logic level. The output of the logic gate is input to the first logic circuit through a feedback loop which is provided between the output and the input of the first logic circuit and which includes the logic gate. According to the circuit construction of the present invention, a flip-flop circuit can be accomplished which is resistant to the radioactive rays such as .alpha. rays and does not cause soft errors.