Patents by Inventor Mitsuo Usami

Mitsuo Usami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040026519
    Abstract: In a wireless IC tag utilizing a wireless IC chip, the wireless IC tag having sufficient stress strength is manufactured economically. There is adopted a structure in which an upper electrode and a lower electrode are respectively formed on a front surface and a rear surface of a wireless IC chip, and the upper electrode is connected to a first conductor and a lower electrode is connected to a second conductor, and the first conductor and the second conductor are connected outside the wireless IC chip. Thereby, it is possible to fabricate the wireless IC tag economically and to ensure the stress strength.
    Type: Application
    Filed: June 27, 2003
    Publication date: February 12, 2004
    Inventors: Mitsuo Usami, Akira Sato
  • Publication number: 20040027180
    Abstract: In order to manufacture a semiconductor device economically and effectively with good manufacturing yield, a power on reset circuit, which sometimes occupies one third of the entire chip area of the semiconductor device for radio frequency identification, is removed to achieve the downsizing of the semiconductor device. A semiconductor device for radio frequency identification comprises one or more flip-flop circuits, wherein an initialization element, functioning to determine that a certain output terminal of the flip-flop circuit is logically fixed to H or L when a power supply voltage is increased, is provided in the flip-flop circuit.
    Type: Application
    Filed: June 20, 2003
    Publication date: February 12, 2004
    Applicant: Hitachi, Ltd
    Inventor: Mitsuo Usami
  • Patent number: 6679428
    Abstract: A carrier case for accommodating paper sheets, cards or the like having radio frequency data carriers attached thereto or watermarked therein. A device is provided for reading out information from the radio frequency data carriers while eliminating the need for externally removing the paper sheets, cards or the like having the radio frequency data carriers attached thereto or watermarked therein. The carrier case is provided therein with an opening for insertion of the data reading device, and is also provided with a movable divider plate. When it is desired to read out data from the radio frequency data carriers, the divider plate is tilted so that the data reading device can read out the data from the data carriers with a good sensitivity in a relationship contacted with the radio frequency data carriers or not contacted therewith.
    Type: Grant
    Filed: February 16, 2001
    Date of Patent: January 20, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Masaya Miura, Yutaka Miyazaki, Mitsuo Usami, Takashi Yoshida
  • Patent number: 6660557
    Abstract: The existing IC cards have a disadvantage of difficulty of mass production because an IC chip is supplied on a substrate one at a time. The present invention provides a method of manufacturing by placing a positioning jig having a plurality of openings each of which has a size fit with a semiconductor device, providing a plurality of semiconductor devices on said jig to house the devices into the openings, and fixing on a substrate then cutting the substrate to provide independent electronic devices. When the semiconductor device is in a form of chip, a support member attached to the chip will facilitate the handling of chips.
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: December 9, 2003
    Assignee: Hitachi, Ltd.
    Inventor: Mitsuo Usami
  • Patent number: 6659353
    Abstract: A method of checking sheets as to forgery thereof, the sheet being provided with an electronic circuit chip from which information can be read out or written and having visible information. The method includes a step of encrypting the visible information of the sheet and storing the encrypted visible information in the electronic circuit chip, and a step of determining discriminatively the authenticity of the sheet by comparing the visible information of the sheet with the information stored in the electronic circuit chip.
    Type: Grant
    Filed: November 27, 2001
    Date of Patent: December 9, 2003
    Assignees: Hitachi, Ltd., Hitachi Research Institute
    Inventors: Chikashi Okamoto, Kazuo Takaragi, Kazutaka Tsuji, Mitsuo Usami, Chizuko Yasunobu, Asahiko Isobe, Yasuhiro Tsunemi, Hiroyuki Yagi
  • Patent number: 6657542
    Abstract: An electronic device, in which a flat plate semiconductor and dumets connected to surface electrodes on the front and back surfaces of the semiconductor and to lead wires are encapsulated in a glass tube.
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: December 2, 2003
    Assignee: Hitachi, Ltd.
    Inventor: Mitsuo Usami
  • Publication number: 20030201522
    Abstract: A semiconductor device manufacturing method is used for packaging a thin semiconductor chip in an economical manner. A semiconductor chip having one electrode terminal, a first member having a first conductor on its surface, and a second member having a second conductor on its surface are prepared. The first and second members are positioned such that the first and second conductors face each other, and the semiconductor chip is held between the members. In this arrangement, one of the first and second conductors is in electrical contact with the first electrode.
    Type: Application
    Filed: April 10, 2003
    Publication date: October 30, 2003
    Inventor: Mitsuo Usami
  • Patent number: 6635968
    Abstract: A semiconductor device manufacturing method is used for packaging a thin semiconductor chip in an economical manner. A semiconductor chip having one electrode terminal, a first member having a first conductor on its surface, and a second member having a second conductor on its surface are prepared. The first and second members are positioned such that the first and second conductors face each other, and the semiconductor chip is held between the members. In this arrangement, one of the first and second conductors is in electrical contact with the first electrode.
    Type: Grant
    Filed: February 5, 2001
    Date of Patent: October 21, 2003
    Assignee: Hitachi, Ltd.
    Inventor: Mitsuo Usami
  • Patent number: 6617172
    Abstract: The present invention aims to economically implement an ultra-compact semiconductor device having an identification number according to the efficient utilization of an electron-beam writing method. A memory for identifying a 128-bit identification number, which makes use of a transistor, is configured by each contact hole selectively defined by an electron-beam writing method. A plane long-side size of a semiconductor chip is set to 0.5 mm or less. The contact holes are defined simultaneously with contact holes for peripheral circuits. In addition, the plane long-side size of the semiconductor chip is set smaller than the thickness of a wafer prior to the start of its manufacture and set larger than the thickness of the post-thinning wafer. Otherwise, the same data as a barcode is further stored in the memory. Additionally, data obtained by enciphering the identification number is used to test or inspect the semiconductor chip.
    Type: Grant
    Filed: August 31, 2001
    Date of Patent: September 9, 2003
    Assignee: Hitachi, Ltd.
    Inventor: Mitsuo Usami
  • Patent number: 6604234
    Abstract: In a method of designing/manufacturing a plurality of semiconductor integrated circuit devices having built-in ROMs each storing different data on a single wafer, a ROM pattern is formed in combination with a pattern that is common to a plurality of semiconductor integrated circuit devices other than the ROM pattern.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: August 5, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Toshio Suzuki, Mitsuo Usami
  • Patent number: 6588672
    Abstract: A semiconductor device is provided which effectively prevents forgery or alteration of IC cards or the like handling important information. Electrodes each having an unshaped irregular surface are provided, respectively, on the IC chip side and the substrate side. The electrodes are connected to each other, with the IC chip facing downward. Connection resistance is employed as a Key code by subjecting the capacitance between the electrodes to A/D conversion. This serves to prevent the duplication of IC cards or the like by employing the connection resistance having a random value as the key code of cryptograph.
    Type: Grant
    Filed: January 28, 2000
    Date of Patent: July 8, 2003
    Assignee: Hitachi, Ltd.
    Inventor: Mitsuo Usami
  • Patent number: 6589855
    Abstract: The semiconductor wafer is made thin without any cracks and warp under good workability. The semiconductor wafer thinning process includes the first step of preparing a carrier 1 formed of a base 1a and a suction pad 1b provided on one surface of the base 1a or formed of a base film with an adhesive, the second step of bonding a semiconductor wafer to the carrier 1 in such a manner that a rear surface of the semiconductor wafer 2 with no circuit elements formed therein is opposite to the carrier to form a wafer composite 10, and the third step of holding the carrier of the wafer composite 10 with its semiconductor wafer 2 side up and spin-coating an etchant on the rear surface of the semiconductor wafer 2 thereby to make the semiconductor wafer 2 thin.
    Type: Grant
    Filed: November 26, 2001
    Date of Patent: July 8, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Toshio Miyamoto, Kunihiro Tsubosaki, Mitsuo Usami
  • Patent number: 6589818
    Abstract: A semiconductor chip (105′) and a substrate (102) are bonded with an organic adhesive layer (409) containing conductive particles (406), and a pad (405) and an electrode (412) are mutually, electrically connected through the conductive particles (406). The semiconductor chip (105′) is formed by contacting a semiconductor wafer (105) attached to a tape (107) with an etchant while rotating the semiconductor wafer (105) within an in-plane direction at a high speed or reciprocating the wafer (105) laterally to uniformly etch the semiconductor wafer (105) thereby reducing the thickness thereof, and dicing the thus reduced wafer. The resultant thin chip (105′) is hot-pressed by means of a heating head (106) for bonding on the substrate (102). In this way, a thin semiconductor chip can be formed stably at low costs and bonded on a substrate without causing any crack of the chip, thereby obtaining a semiconductor device which is unlikely to break owing to the bending stress from outside.
    Type: Grant
    Filed: October 1, 2002
    Date of Patent: July 8, 2003
    Assignee: Hitachi. Ltd.
    Inventors: Mitsuo Usami, Kunihiro Tsubosaki, Kunihiko Nishi
  • Patent number: 6573158
    Abstract: The semiconductor wafer is made thin without any cracks and warp under good workability. The semiconductor wafer thinning process includes the first step of preparing a carrier 1 formed of a base 1a and a suction pad 1b provided on one surface of the base 1a or formed of a base film with an adhesive, the second step of bonding a semiconductor wafer to the carrier 1 in such a manner that a rear surface of the semiconductor wafer 2 with no circuit elements formed therein is opposite to the carrier to form a wafer composite 10, and the third step of holding the carrier of the wafer composite 10 with its semiconductor wafer 2 side up and spin-coating an etchant on the rear surface of the semiconductor wafer 2 thereby to make the semiconductor wafer 2 thin.
    Type: Grant
    Filed: November 26, 2001
    Date of Patent: June 3, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Toshio Miyamoto, Kunihiro Tsubosaki, Mitsuo Usami
  • Publication number: 20030027376
    Abstract: A semiconductor chip (105′) and a substrate (102) are bonded with an organic adhesive layer (409) containing conductive particles (406), and a pad (405) and an electrode (412) are mutually, electrically connected through the conductive particles (406).
    Type: Application
    Filed: October 1, 2002
    Publication date: February 6, 2003
    Inventors: Mitsuo Usami, Kunihiro Tsubosaki, Kunihiko Nishi
  • Patent number: 6514796
    Abstract: A semiconductor chip (105′) and a substrate (102) are bonded with an organic adhesive layer (409) containing conductive particles (406), and a pad (405) and an electrode (412) are mutually, electrically connected through the conductive particles (406). The semiconductor chip (105′) is formed by contacting a semiconductor wafer (105) attached to a tape (107) with an etchant while rotating the semiconductor wafer (105) within an in-plane direction at a high speed or reciprocating the wafer (105) laterally to uniformly etch the semiconductor wafer (105) thereby reducing the thickness thereof, and dicing the thus reduced wafer. The resultant thin chip (105′) is hot-pressed by means of a heating head (106) for bonding on the substrate (102). In this way, a thin semiconductor chip can be formed stably at low costs and bonded on a substrate without causing any crack of the chip, thereby obtaining a semiconductor device which is unlikely to break owing to the bending stress from outside.
    Type: Grant
    Filed: December 5, 2000
    Date of Patent: February 4, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Mitsuo Usami, Kunihiro Tsubosaki, Kunihiko Nishi
  • Patent number: 6486541
    Abstract: A thin-film semiconductor device comprising at least a semiconductor element and a wiring is disclosed. A thin film of a protective insulating material is formed on the lower surface of the semiconductor element, and a substrate is bonded on the lower surface of the thin film. A method for fabricating the thin-film semi-conductor device is also disclosed, in which a thin-film semiconductor circuit is formed on a silicon-on-insulator wafer, the silicon substrate on the reverse side of the silicon-on-insulator wafer is etched off, a thin-film semiconductor chip is formed and attached to the of substrate, and the thin-film semiconductor chip and the substrate are wired to each other by printing.
    Type: Grant
    Filed: September 18, 2001
    Date of Patent: November 26, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Mitsuo Usami, Takashi Tase
  • Publication number: 20020130402
    Abstract: An electronic device, in which a flat plate semiconductor and dumets connected to surface electrodes on the front and back surfaces of the semiconductor and to lead wires are encapsulated in a glass tube.
    Type: Application
    Filed: August 29, 2001
    Publication date: September 19, 2002
    Applicant: Hitachi, Ltd.
    Inventor: Mitsuo Usami
  • Patent number: 6440773
    Abstract: An IC card strong against bending and with a thin semiconductor chip mounted thereon is disclosed which is further provided with a reinforcing plate to reduce damage of the semiconductor chip caused by a point pressure. The IC card is employable even under a mechanically severe environment and is thus highly reliable.
    Type: Grant
    Filed: June 12, 2000
    Date of Patent: August 27, 2002
    Assignee: Hitachi, Ltd.
    Inventor: Mitsuo Usami
  • Publication number: 20020074666
    Abstract: The present invention aims to economically implement an ultra-compact semiconductor device having an identification number according to the efficient utilization of an electron-beam writing method.
    Type: Application
    Filed: August 31, 2001
    Publication date: June 20, 2002
    Inventor: Mitsuo Usami