Patents by Inventor Mitsuru Chida

Mitsuru Chida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120013682
    Abstract: Provided is a liquid ejection head, including: a flow path forming member including: an ejection orifice for ejecting liquid therefrom; and a liquid flow path communicated with the ejection orifice; a silicon substrate including a supply port for supplying the liquid to the liquid flow path; and a protective film which is formed on a wall surface of the supply port and which is formed of an organic resin which is the same as a material of a member forming the flow path forming member.
    Type: Application
    Filed: June 28, 2011
    Publication date: January 19, 2012
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Mitsuru Chida, Satoshi Ibe, Hiroto Komiyama, Yoshinori Tagawa
  • Publication number: 20110141197
    Abstract: When an insulating layer is provided in order to protect an energy generating element, there arises a possibility that the layer dissolves in a contacting liquid. Therefore, in order to eject liquid, a first protection layer containing metal is provided on the insulating layer facing a substrate for a liquid-ejection head and a second protection layer containing metal is provided on the surface of a liquid supply port to which a base containing silicon is exposed.
    Type: Application
    Filed: December 15, 2010
    Publication date: June 16, 2011
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Hiroto Komiyama, Yoshinori Tagawa, Satoshi Ibe, Mitsuru Chida, Kazuhiro Asai
  • Patent number: 7901045
    Abstract: The present invention provides an ink jet recording head which includes a substrate, an energy generating element which is disposed on the substrate and generates energy for discharging a liquid, an electrode which is disposed on the substrate and is electrically connected to the energy generating element, a passage-forming member which is disposed on the substrate, an adhesion layer which is disposed on the substrate and facilitates adhesion between the passage-forming member and the substrate, and a bump disposed on the electrode. The area of an upper surface of the bump is larger than the area of a lower surface of the bump, the lower surface being located on the substrate side, the upper surface being located opposite the lower surface, and a side face of the bump is covered with the adhesion layer. Thereby, a protective film is formed around the bump.
    Type: Grant
    Filed: January 30, 2008
    Date of Patent: March 8, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazuya Abe, Kenji Ono, Toshiyasu Sakai, Hiroyuki Abo, Noriyasu Ozaki, Mitsuru Chida
  • Publication number: 20110020966
    Abstract: A method for processing a silicon substrate includes preparing a first silicon substrate including an etching mask layer including first and second opening portions; forming a first recess in a portion of the silicon substrate corresponding to a region in the first opening portion; etching the silicon substrate by crystal anisotropic etching through the etching mask layer with an etching apparatus and an etchant, the etching proceeding in the first and second opening portions to form a through hole in a position corresponding to the first opening portion and to form a second recess in a position corresponding to the second opening portion; calculating an etching rate of the silicon substrate in terms of the etchant by using the second recess; and determining, by using the calculated etching rate, an etching condition for etching another silicon substrate with the etching apparatus after the etching of the first silicon substrate.
    Type: Application
    Filed: July 19, 2010
    Publication date: January 27, 2011
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Mitsuru Chida, Keiji Edamatsu, Toshiyasu Sakai, Jun Yamamuro
  • Publication number: 20090302502
    Abstract: Provided is a process of producing a liquid discharge head having a substrate, a passage-forming member, and a patterned layer. The process includes providing a resin layer on a substrate; providing a resist pattern on the resin layer for patterning the resin layer; forming a patterned layer by patterning the resin layer using the resist pattern as a mask; providing a layer for forming a passage pattern having a shape of passage on the resist pattern lying on the patterned layer; forming a passage pattern by patterning the layer for forming a passage pattern; removing the resist pattern; providing a passage-forming member so as to cover the passage pattern and the patterned layer; and removing the passage pattern to give the passage.
    Type: Application
    Filed: June 4, 2009
    Publication date: December 10, 2009
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Hiroyuki Abo, Masaki Ohsumi, Toshiyasu Sakai, Noriyasu Ozaki, Mitsuru Chida, Kazuya Abe
  • Publication number: 20090065474
    Abstract: A method for manufacturing a liquid-ejection head substrate including a silicon substrate having a supply port for supplying liquid is provided. The method includes: forming an etching mask layer on a surface of the silicon substrate, the etching mask layer having an opening in a portion corresponding to the supply port; forming a first recess in the surface of the silicon substrate by anisotropically etching the silicon substrate through the opening in the etching mask layer; forming a second recess that extends toward the other surface of the silicon substrate, in a surface of the first recess in the silicon substrate; and forming the supply port by anisotropically etching the silicon substrate from the surface provided with the second recess.
    Type: Application
    Filed: September 5, 2008
    Publication date: March 12, 2009
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Mitsuru Chida, Toshiyasu Sakai, Noriyasu Ozaki, Hiroyuki Abo, Kazuya Abe, Kenji Ono
  • Publication number: 20080180487
    Abstract: The present invention provides an ink jet recording head which includes a substrate, an energy generating element which is disposed on the substrate and generates energy for discharging a liquid, an electrode which is disposed on the substrate and is electrically connected to the energy generating element, a passage-forming member which is disposed on the substrate, an adhesion layer which is disposed on the substrate and facilitates adhesion between the passage-forming member and the substrate, and a bump disposed on the electrode. The area of an upper surface of the bump is larger than the area of a lower surface of the bump, the lower surface being located on the substrate side, the upper surface being located opposite the lower surface, and a side face of the bump is covered with the adhesion layer. Thereby, a protective film is formed around the bump.
    Type: Application
    Filed: January 30, 2008
    Publication date: July 31, 2008
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Kazuya Abe, Kenji Ono, Toshiyasu Sakai, Hiroyuki Abo, Noriyasu Ozaki, Mitsuru Chida
  • Patent number: 6884666
    Abstract: A current path pattern of semiconductor material is formed on the insulating principal surface of a substrate. A gate pattern three-dimensionally crosses the current path pattern in first and second cross areas. A channel region of the current path pattern is defined in an area superposed upon by the gate pattern. A gate insulating film is disposed between the current path pattern and gate pattern. The current path pattern has a lightly doped drain structure on both sides of the channel region in the first cross area, and is not provided with the lightly doped drain structure in regions in contact with the channel region in the second cross area. TFTs are provided having a small off-current and being not necessary for high precision position alignment during manufacture processes even if a gate length is short.
    Type: Grant
    Filed: July 21, 2003
    Date of Patent: April 26, 2005
    Assignee: Fujitsu Limited
    Inventors: Michiko Takei, Yasuyoshi Mishima, Mitsuru Chida, Kohta Yoshikawa
  • Publication number: 20040016927
    Abstract: A current path pattern of semiconductor material is formed on the insulating principal surface of a substrate. A gate pattern three-dimensionally crosses the current path pattern in first and second cross areas. A channel region of the current path pattern is defined in an area superposed upon by the gate pattern. A gate insulating film is disposed between the current path pattern and gate pattern. The current path pattern has a lightly doped drain structure on both sides of the channel region in the first cross area, and is not provided with the lightly doped drain structure in regions in contact with the channel region in the second cross area. TFTs are provided having a small off-current and being not necessary for high precision position alignment during manufacture processes even if a gate length is short.
    Type: Application
    Filed: July 21, 2003
    Publication date: January 29, 2004
    Applicant: Fujitsu Limited
    Inventors: Michiko Takei, Yasuyoshi Mishima, Mitsuru Chida, Kohta Yoshikawa
  • Patent number: 6628349
    Abstract: A liquid crystal display substrate including gate and drain bus lines that are electrically insulated from each other at cross areas, pixel electrodes between the cross areas, and first thin film transistors connecting corresponding drain bus lines and pixel electrodes. Each first thin film transistor includes a channel region where current flows in a first direction, and first and second impurity doped regions of, respectively, first and second impurity concentrations. The first and second doped regions sandwich the channel region. The second impurity concentration is higher than the first. Also, a second thin film transistor is formed in the peripheral circuit area, and includes a channel region where current flows in a second direction that is perpendicular to the first direction. Third impurity doped regions, disposed on both sides of the channel region, have a third impurity concentration.
    Type: Grant
    Filed: August 30, 2000
    Date of Patent: September 30, 2003
    Assignee: Fujitsu Limited
    Inventors: Michiko Takei, Yasuyoshi Mishima, Mitsuru Chida, Kohta Yoshikawa
  • Publication number: 20030119230
    Abstract: A current path pattern of semiconductor material is formed on the insulating principal surface of a substrate. A gate pattern three-dimensionally crosses the current path pattern in first and second cross areas. A channel region of the current path pattern is defined in an area superposed upon by the gate pattern. A gate insulating film is disposed between the current path pattern and gate pattern. The current path pattern has a lightly doped drain structure on both sides of the channel region in the first cross area, and is not provided with the lightly doped drain structure in regions in contact with the channel region in the second cross area. TFTs are provided having a small off-current and being not necessary for high precision position alignment during manufacture processes even if a gate length is short.
    Type: Application
    Filed: December 10, 2002
    Publication date: June 26, 2003
    Applicant: Fujitsu Limited
    Inventors: Mitsuru Chida, Kohta Yoshikawa