Patents by Inventor Mitsuru Onodera
Mitsuru Onodera has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220051981Abstract: A power supply conductive trace structure of a semiconductor device includes a first power supply conductive trace in a mesh form provided in a first power supply conductive trace layer, and a second power supply conductive trace provided in a redistribution layer located on or above the first power supply conductive trace to correspond in position to a conductive trace area that is a portion of the first power supply conductive trace and to be connected to the first power supply conductive trace.Type: ApplicationFiled: August 11, 2021Publication date: February 17, 2022Inventor: Mitsuru ONODERA
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Patent number: 9436795Abstract: A method of verifying a layout of a semiconductor integrated circuit is disclosed. The method includes executing a timing analysis of the semiconductor integrated circuit based on first layout information acquired after execution of a layout process of the semiconductor integrated circuit, executing layout correction with respect to the first layout information, comparing the first layout information acquired before the execution of the layout correction and second layout information acquired after the execution of the layout correction to acquire information indicating an RC difference in wires of the semiconductor integrated circuit before and after the execution of the layout correction, and adding, by a computer, an effect due to an increase in delay in the wires resulting from the RC difference to timing information obtained by the timing analysis.Type: GrantFiled: February 11, 2015Date of Patent: September 6, 2016Assignee: SOCIONEXT INC.Inventor: Mitsuru Onodera
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Patent number: 9255966Abstract: A receiver circuit includes a CDR circuit, a jitter generator unit, a test pattern generator unit, and a comparator unit. The jitter generator unit generates jitter having first characteristics (frequency and amplitude). The test pattern generator unit generates a test pattern to which the jitter is added, and supplies the test pattern to the CDR circuit. The comparator unit compares a value outputted from the CDR circuit with an expected value and outputs a comparison result.Type: GrantFiled: February 10, 2014Date of Patent: February 9, 2016Assignee: SOCIONEXT INC.Inventor: Mitsuru Onodera
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Publication number: 20150254392Abstract: A method of verifying a layout of a semiconductor integrated circuit is disclosed. The method includes executing a timing analysis of the semiconductor integrated circuit based on first layout information acquired after execution of a layout process, executing layout correction with respect to the first layout information, comparing the first layout information acquired before the execution of the layout correction and second layout information acquired after the execution of the layout correction to acquire information indicating an RC difference in wires, and adding, by a computer, an effect due to an increase in delay in the wires resulting from the RC difference to timing information obtained by the timing analysis.Type: ApplicationFiled: February 11, 2015Publication date: September 10, 2015Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Mitsuru ONODERA
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Patent number: 9020421Abstract: According to an embodiment, a wireless communication device includes a first wireless communication section, a wireless power receiving section and a wireless control section. The first wireless communication section is configured to transmit and receive a first wireless signal. The wireless power receiving section is configured to receive power by a second wireless signal. The wireless control section is configured to control the first wireless communication section according to a wireless power reception state of the wireless power receiving section. The wireless control section activates the first wireless communication section after wireless power reception by the wireless power receiving section is started.Type: GrantFiled: February 28, 2013Date of Patent: April 28, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Kiyoshi Toshimitsu, Akira Irube, Mitsuru Onodera, Toshiki Miyasaka, Yoshinari Kumaki, Tomoya Horiguchi, Hirotsugu Kajihara, Ichiro Seto
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Publication number: 20140269872Abstract: A receiver circuit includes a CDR circuit, a jitter generator unit, a test pattern generator unit, and a comparator unit. The jitter generator unit generates jitter having first characteristics (frequency and amplitude). The test pattern generator unit generates a test pattern to which the jitter is added, and supplies the test pattern to the CDR circuit. The comparator unit compares a value outputted from the CDR circuit with an expected value and outputs a comparison result.Type: ApplicationFiled: February 10, 2014Publication date: September 18, 2014Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Mitsuru ONODERA
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Patent number: 8713500Abstract: A computer executes a signal delay evaluation program to determine whether reference levels used to define slew rates of a first circuit block are different from those used for a second circuit block that receives an output signal from the first circuit block. The computer corrects an output slew rate of the output signal supplied from the first circuit block to the second circuit block, based on a difference in the reference levels that is found between the first and second circuit blocks.Type: GrantFiled: September 1, 2009Date of Patent: April 29, 2014Assignee: Fujitsu Semiconductor LimitedInventor: Mitsuru Onodera
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Patent number: 8683401Abstract: An information processing device comprises, a physical property value generation unit to generate a plurality of physical property values for changing signal propagation time of a target path including a plurality of circuit elements within a predetermined fluctuation range, an element delay calculation unit to calculate delay time of each of signals passing through the circuit element in accordance with each of the generated physical property values and a propagation time calculation unit to calculate the signal propagation time of the target path on the basis of the delay time of the signals.Type: GrantFiled: July 6, 2011Date of Patent: March 25, 2014Assignee: Fujitsu Semiconductor LimitedInventor: Mitsuru Onodera
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Publication number: 20130324052Abstract: According to an embodiment, a wireless communication device includes a first wireless communication section, a wireless power receiving section and a wireless control section. The first wireless communication section is configured to transmit and receive a first wireless signal. The wireless power receiving section is configured to receive power by a second wireless signal. The wireless control section is configured to control the first wireless communication section according to a wireless power reception state of the wireless power receiving section. The wireless control section activates the first wireless communication section after wireless power reception by the wireless power receiving section is started.Type: ApplicationFiled: February 28, 2013Publication date: December 5, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kiyoshi TOSHIMITSU, Akira IRUBE, Mitsuru ONODERA, Toshiki MIYASAKA, Yoshinari KUMAKI, Tomoya HORIGUCHI, Hirotsugu KAJIHARA, Ichiro SETO
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Patent number: 8504332Abstract: A non-transitory computer-readable recording medium stores therein a program that causes a processor to execute inputting a driving capability value, a lumped-constant capacitance value, and an input capacitance value included in the lumped-constant capacitance value, respectively defined in a circuit model, and further inputting a first delay time of the circuit model, based on the driving capability value and the lumped-constant capacitance value; setting in the circuit model, the driving capability value, the lumped-constant capacitance value, and the input capacitance value; acquiring a second delay time of the circuit model, by providing to a simulator, the circuit model having values set therein; calculating a relative evaluation value for the first delay time and the second delay time; and storing to a storage apparatus and as a delay time correcting coefficient, the relative evaluation value correlated with the driving capability value, the lumped-constant capacitance value, and the input capacitanceType: GrantFiled: June 3, 2010Date of Patent: August 6, 2013Assignee: Fujitsu Semiconductor LimitedInventor: Mitsuru Onodera
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Patent number: 8433022Abstract: A clock data recovery circuit includes a receiving circuit that takes in input data based on a sampling clock, a demultiplexer that converts serial data output from the receiving circuit into parallel data, a clock/data recovery part that detects phase information from the parallel data output from the demultiplexer and generates the sampling clock by adjusting the phase of a reference clock based on the phase information, a data pattern analyzer that carries out frequency analysis of the parallel data output from the demultiplexer, and an aliasing detector that detects a clock recovery state based on the analysis result of the frequency of the parallel data.Type: GrantFiled: May 23, 2011Date of Patent: April 30, 2013Assignee: Fujitsu Semiconductor LimitedInventor: Mitsuru Onodera
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Patent number: 8423944Abstract: A design supporting method includes partitioning a partition path of circuit information into partitioned paths based on a given condition, calculating a variation value of each of the partitioned paths based on variation values on a delay of a cell included in the corresponding partitioned path, calculating a partition propagation delay time of each of the partitioned paths based on the variation value of the corresponding partitioned path, and calculating a source propagation delay time of the source path by merging the propagation delay time of each of the partitioned paths.Type: GrantFiled: December 17, 2009Date of Patent: April 16, 2013Assignee: Fujitsu Semiconductor LimitedInventor: Mitsuru Onodera
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Patent number: 8381146Abstract: A computer-readable, non-transitory medium stores therein a design support program that causes a computer capable of accessing a storage device storing therein for each cell, an output voltage value of the cell, for each elapsed time period from a start of variation of an input voltage applied to the cell, to execute a process. The process includes extracting from the storage device, the output voltage value for each elapsed time period related to an cell under design selected from circuit information of a circuit under design; determining based on a specific voltage value, an extracted elapsed time period to be corrected; adding a time constant of an output from the cell under design to the elapsed time period determined to correction; and outputting the output voltage value for each corrected elapsed time period and the output voltage value for each elapsed time period that is not determined for correction.Type: GrantFiled: March 16, 2011Date of Patent: February 19, 2013Assignee: Fujitsu Semiconductor LimitedInventor: Mitsuru Onodera
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Publication number: 20120039426Abstract: A clock data recovery circuit includes a receiving circuit that takes in input data based on a sampling clock, a demultiplexer that converts serial data output from the receiving circuit into parallel data, a clock/data recovery part that detects phase information from the parallel data output from the demultiplexer and generates the sampling clock by adjusting the phase of a reference clock based on the phase information, a data pattern analyzer that carries out frequency analysis of the parallel data output from the demultiplexer, and an aliasing detector that detects a clock recovery state based on the analysis result of the frequency of the parallel data.Type: ApplicationFiled: May 23, 2011Publication date: February 16, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Mitsuru ONODERA
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Publication number: 20120036490Abstract: An information processing device comprises, a physical property value generation unit to generate a plurality of physical property values for changing signal propagation time of a target path including a plurality of circuit elements within a predetermined fluctuation range, an element delay calculation unit to calculate delay time of each of signals passing through the circuit element in accordance with each of the generated physical property values and a propagation time calculation unit to calculate the signal propagation time of the target path on the basis of the delay time of the signals.Type: ApplicationFiled: July 6, 2011Publication date: February 9, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Mitsuru ONODERA
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Publication number: 20110314433Abstract: A computer-readable, non-transitory medium stores therein a design support program that causes a computer capable of accessing a storage device storing therein for each cell, an output voltage value of the cell, for each elapsed time period from a start of variation of an input voltage applied to the cell, to execute a process. The process includes extracting from the storage device, the output voltage value for each elapsed time period related to an cell under design selected from circuit information of a circuit under design; determining based on a specific voltage value, an extracted elapsed time period to be corrected; adding a time constant of an output from the cell under design to the elapsed time period determined to correction; and outputting the output voltage value for each corrected elapsed time period and the output voltage value for each elapsed time period that is not determined for correction.Type: ApplicationFiled: March 16, 2011Publication date: December 22, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Mitsuru ONODERA
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Publication number: 20110314434Abstract: A computer-readable, non-transitory medium stores therein a design support program that causes a computer capable of accessing a storage device storing therein for each cell, an output voltage value of the cell, for each elapsed time period from a start of variation of an input voltage applied to the cell, to execute a process. The process includes extracting from the storage device, the output voltage value for each elapsed time period related to an cell under design selected from circuit information of a circuit under design; determining based on a specific voltage value, an extracted elapsed time period to be corrected; adding a time constant of an output from the cell under design to the elapsed time period determined to correction; and outputting the output voltage value for each corrected elapsed time period and the output voltage value for each elapsed time period that is not determined for correction.Type: ApplicationFiled: March 16, 2011Publication date: December 22, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Mitsuru ONODERA
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Publication number: 20100318341Abstract: A non-transitory computer-readable recording medium stores therein a program that causes a processor to execute inputting a driving capability value, a lumped-constant capacitance value, and an input capacitance value included in the lumped-constant capacitance value, respectively defined in a circuit model, and further inputting a first delay time of the circuit model, based on the driving capability value and the lumped-constant capacitance value; setting in the circuit model, the driving capability value, the lumped-constant capacitance value, and the input capacitance value; acquiring a second delay time of the circuit model, by providing to a simulator, the circuit model having values set therein; calculating a relative evaluation value for the first delay time and the second delay time; and storing to a storage apparatus and as a delay time correcting coefficient, the relative evaluation value correlated with the driving capability value, the lumped-constant capacitance value, and the input capacitanceType: ApplicationFiled: June 3, 2010Publication date: December 16, 2010Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Mitsuru ONODERA
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Publication number: 20100218153Abstract: A design supporting method includes partitioning a partition path of circuit information into partitioned paths based on a given condition, calculating a variation value of each of the partitioned paths based on variation values on a delay of a cell included in the corresponding partitioned path, calculating a partition propagation delay time of each of the partitioned paths based on the variation value of the corresponding partitioned path, and calculating a source propagation delay time of the source path by merging the propagation delay time of each of the partitioned paths.Type: ApplicationFiled: December 17, 2009Publication date: August 26, 2010Applicant: FUJITSU MICROELECTRONIC LIMITEDInventor: Mitsuru ONODERA
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Publication number: 20090319972Abstract: A computer executes a signal delay evaluation program to determine whether reference levels used to define slew rates of a first circuit block are different from those used for a second circuit block that receives an output signal from the first circuit block. The computer corrects an output slew rate of the output signal supplied from the first circuit block to the second circuit block, based on a difference in the reference levels that is found between the first and second circuit blocks.Type: ApplicationFiled: September 1, 2009Publication date: December 24, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventor: Mitsuru ONODERA