Patents by Inventor Mitsuru Onodera

Mitsuru Onodera has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7243283
    Abstract: A semiconductor device having a plurality of circuits with the same configuration, wherein since expected values in the number corresponding to the number of circuits are not required, operation tests are effectively performed in a short time. The semiconductor device has first, second and third digital filters with the same configuration. To test these digital filters, comparison circuits comparing an output value and an expected value are individually provided per one digital filter. The digital filters and the comparison circuits are daisy-chained such that the output values of the first and second digital filters are input as the expected values of the comparison circuits corresponding to the second and third digital filters, respectively. When the same test signal is input to each digital filter from a built-in self test (BIST) controller, abnormal circuits can be detected based on comparison results of the comparison circuits.
    Type: Grant
    Filed: April 1, 2005
    Date of Patent: July 10, 2007
    Assignee: Fujitsu Limited
    Inventor: Mitsuru Onodera
  • Publication number: 20060107150
    Abstract: A semiconductor device having a plurality of circuits with the same configuration, wherein since expected values in the number corresponding to the number of circuits are not required, operation tests are effectively performed in a short time. The semiconductor device has first, second and third digital filters with the same configuration. To test these digital filters, comparison circuits comparing an output value and an expected value are individually provided per one digital filter. The digital filters and the comparison circuits are daisy-chained such that the output values of the first and second digital filters are inputted as the expected values of the comparison circuits corresponding to the second and third digital filters, respectively. When the same test signal is inputted to each digital filter from a built-in self test (BIST) controller, occurrence of abnormal circuits can be detected based on comparison results of the comparison circuits.
    Type: Application
    Filed: April 1, 2005
    Publication date: May 18, 2006
    Inventor: Mitsuru Onodera