Abstract: A display device includes a frame that includes a front portion, temple portions, and a pad portion, and is mounted on head of an observer, and an image display device attached to the frame. The image display device includes an image forming device, and an optical device on which light emitted from the image forming device is incident and from which the light is emitted toward the observer. One end portion of the optical device is fixed to a temple portion side of the front portion. Other end portion of the optical device is on a pad portion side of the front portion. A light shielding member that prevents external light from being incident on the other end portion of the optical device from above the other end portion of the optical device is attached to the pad portion side of the front portion.

Abstract: A semiconductor memory device includes a memory collar, a repair data analyzer, a BIST block, and a system logic. The memory collar includes a memory cell and a spare cell and have a redundancy function of replacing fail memory cell with the spare cell if fail memory cell exists. The repair data analyzer determines whether or not memory cell included in the memory collar is defective, and generates fail address corresponding to the memory cell determined as being defective. The BIST block operates in synchrony with a first clock signal inputted to a first clock signal terminal in a test operation mode, and controls the operation of the memory collar. The system logic operates in synchrony with a second clock signal inputted to a second clock signal terminal in the test operation mode.

Abstract: A semiconductor memory device includes a memory collar, a repair data analyzer, a BIST block, and a system logic. The memory collar includes a memory cell and a spare cell and have a redundancy function of replacing fail memory cell with the spare cell if fail memory cell exists. The repair data analyzer determines whether or not memory cell included in the memory collar is defective, and generates fail address corresponding to the memory cell determined as being defective. The BIST block operates in synchrony with a first clock signal inputted to a first clock signal terminal in a test operation mode, and controls the operation of the memory collar. The system logic operates in synchrony with a second clock signal inputted to a second clock signal terminal in the test operation mode.

Abstract: A self-developing type of instant camera is equipped with a processing liquid spreading device comprising a pair of pressure-applying processing rollers which ruptures a processing liquid containing pod and distributes a processing liquid in a film unit, a spread controller operative to press and rubs the film unit from one side of the film unit coming out from a film pack so as to spread the processing liquid distributed in the film unit and a guide member, disposed between the spread controller and the film pack, operative to force the film unit from another side of the film unit so as to direct the film unit toward the bite of pressure-applying processing rollers.

Abstract: A p-well region (16) is formed in the main surface area of an n-type semiconductor substrate (11). A potential (V.sub.BB) which is lower than an externally input potential is applied to the p-well region (16). In the surface area of the p-well region (16), a first impurity diffused layer (12) of n-type to which the externally input potential (Vin) is applied and a second impurity diffused layer (13) of n-type to which a reference potential is applied are formed. The first impurity diffused layer (12) serves as the drain region of a first MOS transistor (Q9) of n-channel formed in the p-well region (16) and the second impurity diffused layer (13) serves as the drain region of a second MOS transistor (Q10) of n-channel which is also formed in the p-well region (16). The first and second MOS transistors (Q9 and Q10) constitute the input section of an input circuit.

Abstract: A ferroelectric memory having a memory cell array or a plurality of memory cell arrays, word lines, where each memory cell array includes word lines. The memory also includes a plurality of plate lines, where each memory cell array includes some of the plate lines and the word line corresponds with some of the plate lines, a bit line, a word line select circuit for selecting among the word lines, and plurality of plate line select circuits, where each of the plate line select circuit is coupled to an associated plate line.

Abstract: An apparatus for producing a Fresnel plate has a mold assembly comprising movable and stationary molds coupled with each other. The mold assembly includes a Fresnel forming face formed on the inside of the movable mold. Melted resin is injected into the mold assembly for forming the Fresnel plate. At least one movable slit is formed through, and arranged inside, the movable mold along a circle concentric with the Fresnel plate and in intermittent or continuous fashion. The movable slit is used for blowing compressed air toward the Fresnel plate. The slit closely surrounds the center of the Fresnel plate. Ejector pins surround the Fresnel plate outside its Fresnel forming face.

Abstract: A ferroelectric memory has a memory cell screening test circuit connected to bit lines through switching transistors. In screening, at least one word line is selected, and data is simultaneously written in all memory cells connected to this word line. Since data is not restored after the rewrite, all FRAM cells can be screened under the same condition. By this circuit, a memory cell having a write failure according to the imprint characteristics inherent to the ferroelectric memory is screened.

Abstract: According to this invention, a well region is formed on a semiconductor substrate. An n.sup.+ -type first semiconductor region is formed in the well region, and an input pad for receiving an external signal is connected near the first semiconductor region. This input pad is connected to an input circuit of an integrated circuit constituted by an inverter circuit and to an external terminal for receiving an external signal. N.sup.+ -type second semiconductor regions are formed in the well region located on both sides of the first semiconductor region. A ground potential Vss is applied to these second semiconductor regions. A p.sup.+ -type third semiconductor region is formed around these second semiconductor regions in the well region. The ground potential is applied to the third semiconductor region. Therefore, a parallel circuit formed by a parasitic transistor and a parasitic diode is formed between the input pad and the ground potential.

Abstract: A nonvolatile ferroelectric memory comprises a memory cell array having memory cells arranged as a matrix array and each including a charge transfer transistor having a source or drain region connected to a bit line and a gate connected to a word line and a ferroelectric capacitor for information storage having one electrode connected to a plate line and the other electrode connected to the drain or source region of the charge transfer transistor. A first dummy line is arranged outside a bit line formed at an end of the memory cell array and second dummy bit lines are arranged between the bit line at the end of the memory cell array and the first dummy bit line. Dummy memory cells are connected to the second dummy bit line and have the same in configuration and size as the memory cells connected to the bit line.

Abstract: Circuitry within a ferroelectric memory prevents inversion of the polarization of ferroelectric memory cells caused by a power on reset signal to avoid corruption of data stored therein. A ferroelectric memory includes a memory cell array, a plurality of word lines commonly connected to the gates of the cell transistors in the same row, a plurality of plate lines commonly connected to the plates of the cell capacitors in the same row, a plurality of bit lines commonly connected to one end of the cell transistors in the same row, and a power on reset circuit for generating a power on reset signal of a predetermined level for a predetermined period of time after the power supply is turned on. An erroneous programming prevention circuit within the memory includes a plurality of switching transistors connected between all of the bit lines and plate lines and a plurality of nodes at a predetermined potential.

Abstract: An apparatus for producing a Fresnel plate has a mold assembly comprising movable and stationary molds coupled with each other. The mold assembly includes a Fresnel forming face formed on the inside of the movable mold. Melted resin is injected into the mold assembly for forming the Fresnel plate. At least one movable slit is formed through, and arranged inside, the movable mold along a circle concentric with the Fresnel plate and in intermittent or continuous fashion. The movable slit is used for blowing compressed air toward the Fresnel plate. The slit closely surrounds the center of the Fresnel plate. Ejector pins surround the Fresnel plate outside its Fresnel forming face.

Abstract: Circuitry within a ferroelectric memory prevents inversion of the polarization of ferroelectric memory cells caused by a power on reset signal to avoid corruption of data stored therein. A ferroelectric memory includes a memory cell array, a plurality of word lines commonly connected to the gates of the cell transistors in the same row, a plurality of plate lines commonly connected to the plates of the cell capacitors in the same row, a plurality of bit lines commonly connected to one end of the cell transistors in the same row, and a power on reset circuit for generating a power on reset signal of a predetermined level for a predetermined period of time after the power supply is turned on. An erroneous programming prevention circuit within the memory includes a plurality of switching transistors connected between all of the bit lines and plate lines and a plurality of nodes at a predetermined potential.

Abstract: A single-use instant camera includes a main body, having the taking lens and the shutter mechanism. A film unit containing chamber is formed in the main body, and contains a plurality of instant the film units stacked on one another. The containing chamber is opened toward a rear and has a front wall. An exposure aperture is formed in the front wall, and receives the image-recording portion of the film units, to provide the film units with exposure to light a entered through the taking lens from an object to be photographed. A front cover is disposed in front of the main body to cover the main body. An advancing claw mechanism is disposed between the front cover and the main body, and advances an exposed one of the film units to be exited. A flash device is disposed between the front cover and the main body, and applies illuminating light to the object. A back lid is disposed behind the containing chamber, is engaged with the main body, and closes the containing chamber.

Abstract: A single-use instant camera includes a main body, having the taking lens and the shutter mechanism. A film unit containing chamber is formed in the main body, and contains a plurality of instant film units stacked on one another. The containing chamber is opened toward a rear and has a front wall. An exposure aperture is formed in the front wall, and receives the image-recording portion of the film units, to provide the film units with exposure to light entered through the taking lens from an object to be photographed. A front cover is disposed in front of the main body to cover the main body. An advancing claw mechanism is disposed between the front cover and the main body, and advances an exposed one of the film units to be exited. A flash device is disposed between the front cover and the main body, and applies illuminating light to the object. A back lid is disposed behind the containing chamber, is engaged with the main body, and closes the containing chamber.

Abstract: According to the invention, a well region is formed on a semiconductor substrate. An n.sup.+ -type first semiconductor region is formed in the well region, and an input pad for receiving an external signal is connected near the first semiconductor region. This input pad is connected to an input circuit of an integrated circuit constituted by an inverter circuit and to an external terminal for receiving an external signal. N.sup.+ -type second semiconductor regions are formed in the well region located on both sides of the first semiconductor region. A ground potential Vss is applied to these second semiconductor regions. A p.sup.+ -type third semiconductor region is formed around these second semiconductor regions in the well region. The ground potential is applied to the third semiconductor region. Therefore, a parallel circuit formed by a parasitic transistor and a parasitic diode is formed between the input pad and the ground potential.

Abstract: According to this invention, word line drive circuits are respectively connected to memory cell arrays. These memory cell arrays are respectively driven by the word line drive circuits. Therefore, the potential of a normal word line selected simultaneously with a word line in which a failure has occurred and which is included in a memory cell array can be prevented from being decreased so as to prevent the normal word line from the failure. For this reason, the yield can be increased without unnecessarily using a redundancy circuit.

Abstract: An instant camera is used with a film unit, in which a solution pod contains processing solution. The camera has first and second rotatable spreading rollers, which apply pressure to the film unit. When rotated the spreading rollers squeeze the pod, exit the film unit, and spread the solution. At least the first spreading roller is shaped to have convexity at a center like a barrel which meets0.5.delta..ltoreq.D.sub.1 -D.sub.2 .ltoreq.4 .delta.where D.sub.1 is a diameter of a center of the first spreading roller, D.sub.2 is a diameter of ends of the first spreading roller, and .delta. is an amount at which the roller center is flexed relative to the roller ends and which meets.delta.=WL.sup.3 /(3.pi./D.sub.2.sup.4 .multidot.E)where E is Young's modulus of material of the first spreading roller, L is a length of the first spreading roller, and W is load applied between the two spreading rollers. At least the first spreading roller is of the material meetingE.gtoreq.WL.sup.3 /(3.pi.D.sub.2.sup.4 .multidot.

Abstract: A transparent substrate and a method of producing the same suitable especially for an optical system for an optical data recording medium using a linearly polarized light as a data reading light such as magneto-optical recording medium drive unit and an optical data recording medium for reading data using a linearly polarized light.

Abstract: A semiconductor memory device is disclosed which comprises a regular row/column memory cell array having blocks obtained by dividing the memory cell array in the column and row directions, .Iadd.the blocks each being further divided in the column direction to form a plurality of sections, .Iaddend.a first peripheral circuit .?.irregularly.!. provided between the blocks divided in the column direction, a second peripheral circuit provided between the blocks divided in the row direction and including a first decoder, a third peripheral circuit provided between the first peripheral circuit and the respective block and including a second decoder, and .?.a fourth peripheral circuit provided at the marginal portion of the memory cell array and including bonding pads and input protection circuit.!. .Iadd.sense amplifiers provided between neighboring sections in each of the blocks.Iaddend..