Semiconductor memory device
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Claims
3. The semiconductor memory device according to claim 1, wherein said first decoder is shared by adjacent blocks in said memory cell array.
8. The semiconductor memory device according to claim 6, wherein said first decoder is shared by adjacent blocks in said memory cell array.
13. The semiconductor memory device according to claim 11, wherein said first decoder is shared by adjacent blocks in the memory.Iadd.cell.Iaddend.array.
Referenced Cited
U.S. Patent Documents
Foreign Patent Documents
Other references
0 130 798 | January 1985 | EPX |
60-9152 | January 1985 | JPX |
60-251643 | December 1985 | JPX |
3-214669 | September 1991 | JPX |
- Syuso Fujii et al., "A 45ns 16Mb DRAM with Triple-Well Structure"; 1989 IEEE International Solid-State Circuits Conference; pp. 248-249 and 354. Tomio Nakano et al., "A Sub-100 ns 256K DRAM With Open Bit Line Scheme"; IEEE J. Solid-State Circuits, pp. 452-456; vol. SC-18, No. 5 (1983).
Patent History
Patent number: RE36236
Type: Grant
Filed: Jun 7, 1995
Date of Patent: Jun 29, 1999
Assignee: Kabushiki Kaisha Toshiba (Kawasaki)
Inventors: Mitsuru Shimizu (Sakura), Syuso Fujii (Hopewell Jct, NY)
Primary Examiner: Terrell W. Fears
Law Firm: Banner & Witcoff
Application Number: 8/475,378
Type: Grant
Filed: Jun 7, 1995
Date of Patent: Jun 29, 1999
Assignee: Kabushiki Kaisha Toshiba (Kawasaki)
Inventors: Mitsuru Shimizu (Sakura), Syuso Fujii (Hopewell Jct, NY)
Primary Examiner: Terrell W. Fears
Law Firm: Banner & Witcoff
Application Number: 8/475,378
Classifications
Current U.S. Class:
Format Or Disposition Of Elements (365/51);
Insulated Gate Devices (365/182);
365/18901;
Noise Suppression (365/206)
International Classification: G11C 1300;
International Classification: G11C 1300;