Abstract: A joint position estimation device including a memory, and a processor connected to the memory. The processor executes a process including estimating, by a first DNN for which a first parameter determined by learning of the first DNN has been set, a body part region of the animal with respect to input image to be processed; and estimating, by the second DNN for which a second parameter determined by learning of the second DNN has been set, a first joint position and a second joint position in each of the body part region estimated by the first DNN and a plural body parts region in which a plurality of the body part regions are connected.

Abstract: An operation processing device includes: a memory; and a processor coupled to the memory and configured to: acquire statistical information on distribution of bits in fixed point number data after execution of an instruction on the fixed point number data; and update a decimal point position of the fixed point number data.

Abstract: An apparatus for data output control includes: an encryption executing circuit configured to receive first data from a processor with a control signal indicating whether the first data is to be encrypted, and encrypt the first data when the control signal indicates that the first data is to be encrypted; a selection circuit configured to output any of the encrypted first data and second data; and an output control unit configured to set a frequency of second timing to be smaller than a frequency of first timing, and transmit a signal to the selection circuit instructing that the second data be outputted at the second timing, in a case where the second data is received from the processor.

Abstract: An operation processing apparatus includes a memory and a processor coupled to the memory. The processor executes an operation according to an operation instruction, acquires statistical information for a distribution of bits in fixed point data after an execution of an operation for the fixed point data according to an acquisition instruction, and outputs the statistical information to a register designated by the acquisition instruction.

Abstract: A simulation method performed by a computer for simulating operations by a plurality of cores based on resource access operation descriptions on the plurality of cores, the method includes steps of: extracting a resource access operation description on at least one core of the plurality of cores by executing simulation for the one core; and, under a condition where the one core and a second core among the plurality of cores have a specific relation in execution processing, generating a resource access operation description on the second core from the resource access operation description on the one core by reflecting an address difference between an address of a resource to which the one core accesses and an address of a resource to which the second core accesses.

Abstract: A non-transitory computer-readable recording medium having stored therein an information processing program for causing a computer to execute a process includes: calculating, by using an image including an object having a plurality of joints and having a plurality of frames consecutive in time, a probability distribution of a joint position of the object in each frame; calculating a transition score by evaluating a consistency of a transition of a joint of the plurality of joints using transition information of the joint among different frames; and estimating a pose of the object from a score of the probability distribution and the transition score.

Abstract: An information processing device includes: a memory; and a processor coupled to the memory and configured to: estimate a first position of a first joint in a two-dimensional plane based on a color image, and estimate a first positional relationship between the first joint and a second joint coupled to the first joint via a portion in the two-dimensional plane; estimate a second position of the first joint in the two-dimensional plane based on a depth image indicating respective depths of the first joint and the second joint, and estimate a second positional relationship between the first joint and the second joint in a three-dimensional space; and estimate a third position of the first joint in the two-dimensional plane and posture of the portion in the three-dimensional space based on the first position, the first positional relationship the second position, and the second positional relationship.

Abstract: A processor includes: a plurality of processor cores; and an internal memory configured to be accessed from the plurality of processor cores, wherein an arithmetic circuit provided in any of the plurality of processor cores includes: a plurality of first registers provided in a first stage of the arithmetic circuit, a regular addition circuit including a first adder and a second register, the first adder being configured to add a plurality of outputs of the plurality of first registers, the second register being configured to be provided in a second stage and latch an output of the first adder, an overtaking addition circuit including a second adder, the second adder being configured to add a plurality of outputs of the plurality of first registers, and a synthesis circuit including a third adder and a third register.

Abstract: A processor circuit includes: multiple processor cores; multiple individual memories; multiple shared memories; multiple memory control circuits; multiple selectors; and a control core; wherein when an address of the read request from the first processor associated with a specific memory control circuit is identical to the transfer source address, the specific memory control circuit controls the transfer data based on the read request to be transferred to the transfer destination address via a specific selector of the multiple selectors in which the transfer selection information is set, wherein, when the control core sets read selection information in each of the multiple selectors, read data is read by one of the first processor core and the first adjacent processor core from the associated shared memory via a specific selector of the multiple selectors in which the read selection information is set.

Abstract: A processor includes: a first memory configured to store image data including pixel data of a plurality of pixels that are two-dimensionally arranged; a second memory configured to store neighborhood matrix image data including pixel data of a neighborhood matrix; and a format converter that includes (a) a readout circuit configured to read out the image data from the first memory, (b) a padding arithmetic unit configured to receive the read-out image data, select pixel data of the received read-out image data and padding data inserted at periphery of the plurality of pixels in accordance with mask values of a padding mask, and generate the neighborhood matrix image data including the pixel data and the padding data, and (c) a writing circuit configured to write the neighborhood matrix image data to the second memory.

Abstract: A joint position estimation device including a memory, and a processor connected to the memory. The processor executes a process including estimating, by a first DNN for which a first parameter determined by learning of the first DNN has been set, a body part region of the animal with respect to input image to be processed; and estimating, by the second DNN for which a second parameter determined by learning of the second DNN has been set, a first joint position and a second joint position in each of the body part region estimated by the first DNN and a plural body parts region in which a plurality of the body part regions are connected.

Abstract: An operation processing device includes: a memory; and a processor coupled to the memory and configured to: acquire statistical information on distribution of bits in fixed point number data after execution of an instruction on the fixed point number data; and update a decimal point position of the fixed point number data.

Abstract: An apparatus for data output control includes: an encryption executing circuit configured to receive first data from a processor with a control signal indicating whether the first data is to be encrypted, and encrypt the first data when the control signal indicates that the first data is to be encrypted; a selection circuit configured to output any of the encrypted first data and second data; and an output control unit configured to set a frequency of second timing to be smaller than a frequency of first timing, and transmit a signal to the selection circuit instructing that the second data be outputted at the second timing, in a case where the second data is received from the processor.

Abstract: An information processing device includes: a memory; and a processor coupled to the memory and configured to: estimate a first position of a first joint in a two-dimensional plane based on a color image, and estimate a first positional relationship between the first joint and a second joint coupled to the first joint via a portion in the two-dimensional plane; estimate a second position of the first joint in the two-dimensional plane based on a depth image indicating respective depths of the first joint and the second joint, and estimate a second positional relationship between the first joint and the second joint in a three-dimensional space; and estimate a third position of the first joint in the two-dimensional plane and posture of the portion in the three-dimensional space based on the first position, the first positional relationship the second position, and the second positional relationship.

Abstract: An operation processing apparatus includes a memory and a processor coupled to the memory. The processor executes an operation according to an operation instruction, acquires statistical information for a distribution of bits in fixed point data after an execution of an operation for the fixed point data according to an acquisition instruction, and outputs the statistical information to a register designated by the acquisition instruction.

Abstract: A processor includes: a plurality of processor cores; and an internal memory configured to be accessed from the plurality of processor cores, wherein an arithmetic circuit provided in any of the plurality of processor cores includes: a plurality of first registers provided in a first stage of the arithmetic circuit, a regular addition circuit including a first adder and a second register, the first adder being configured to add a plurality of outputs of the plurality of first registers, the second register being configured to be provided in a second stage and latch an output of the first adder, an overtaking addition circuit including a second adder, the second adder being configured to add a plurality of outputs of the plurality of first registers, and a synthesis circuit including a third adder and a third register.

Abstract: A processor circuit includes: multiple processor cores; multiple individual memories; multiple shared memories; multiple memory control circuits; multiple selectors; and a control core; wherein when an address of the read request from the first processor associated with a specific memory control circuit is identical to the transfer source address, the specific memory control circuit controls the transfer data based on the read request to be transferred to the transfer destination address via a specific selector of the multiple selectors in which the transfer selection information is set, wherein, when the control core sets read selection information in each of the multiple selectors, read data is read by one of the first processor core and the first adjacent processor core from the associated shared memory via a specific selector of the multiple selectors in which the read selection information is set.

Abstract: A processor includes; a first memory configured to store image data including pixel data of a plurality of pixels that are two-dimensionally arranged; a second memory configured to store neighborhood matrix image data including pixel data of a neighborhood matrix; and a format converter that includes (a) a readout circuit configured to read out the image data from the first memory, (b) a padding arithmetic unit configured to receive the read-out image data, select pixel data of the received read-out image data and padding data inserted at periphery of the plurality of pixels in accordance with mask values of a padding mask, and generate the neighborhood matrix image data including the pixel data and the padding data, and (c) a writing circuit configured to write the neighborhood matrix image data to the second memory.

Abstract: A communication system includes a first device including a first memory for storing first data, and a processor configured to generate second data according to the first data and store the second data in a second memory; a second device including a processor configured to transmit the second data, stored in the second memory to a first server; and a control device including a processor configured to exclusively turn on the first device and the second device.

Abstract: A simulation method performed by a computer for simulating operations by a plurality of cores based on resource access operation descriptions on the plurality of cores, the method includes steps of: extracting a resource access operation description on at least one core of the plurality of cores by executing simulation for the one core; and, under a condition where the one core and a second core among the plurality of cores have a specific relation in execution processing, generating a resource access operation description on the second core from the resource access operation description on the one core by reflecting an address difference between an address of a resource to which the one core accesses and an address of a resource to which the second core accesses.