Abstract: A method for making a dual-gate oxide field effect transistors is achieved. The method utilizes a patterned thin silicon nitride layer and a single rapid thermal oxidation step to form a thicker gate oxide for memory and peripheral circuits while forming a thin nitrogen rich gate oxide for high-performance logic circuits. After forming STI around the logic and memory call areas and removing any native oxide, a thin CVD silicon nitride layer is deposited. The Si3N4 is patterned to leave portions over the logic device areas. A single rapid thermal oxidation process is performed to grow a thicker gate oxide on the exposed memory areas while concurrently the Si3N4 is slowly converted to a nitrogen-rich oxide and forms a thinner gate oxide on the logic device areas. The thinner nitrogen-rich gate oxide also retards boron diffusion to make more stable devices.

Abstract: A method of simultaneously forming a high-k metal oxide dielectric layer and a gate oxide dielectric layer comprising the following steps. A structure having isolation regions which separate the structure into at least one core device active region and one I/O active region is provided. A buffer layer is formed over the structure and the isolation regions. A metal containing layer is formed over the buffer layer. The metal containing layer and the buffer layer are patterned to: form an exposed patterned metal containing layer within the at least one core device action region; and expose the structure within the at least one I/O active region. The exposed patterned metal containing layer and the exposed structure within the at least one I/O active region are oxidized to simultaneously form: the high-k metal oxide dielectric layer within the at least one core device active region; and the gate oxide dielectric layer within the at least one I/O active region.

Abstract: Within a method for forming a series of gate dielectric layers having a plurality of thicknesses upon a semiconductor substrate, there is sequentially selectively stripped only a series of sacrificial gate dielectric layers only in locations where new gate dielectric layers are desired to be formed, rather masking a only a portion of a partially sacrificial gate dielectric layer which is desired to be retained and stripping a sacrificial remainder of the gate dielectric layer. By employing the sequential selective stripping method, a semiconductor integrated circuit microelectronic fabrication is formed with enhanced reliability insofar as there is attenuated over etching into isolation regions which separate active regions of a semiconductor substrate.

Abstract: A method for forming upon a semiconductor substrate employed within a microelectronics fabrication a composite gate insulating layer of MOS device comprising a silicon oxide dielectric layer and a high-K dielectric layer. The method employs thermal oxidation of a silicon semiconductor substrate to form an initial silicon oxide dielectric layer. A RPN plasma method is employed to form a layer of silicon nitride high-k dielectric material partly into the silicon oxide dielectric layer. The composite dielectric layer is dielectrically equivalent to the initial silicon oxide dielectric layer, with equivalent performance, reliability and manufacturability of the MOS device.

Abstract: A process for forming a nitrogen enriched ultra thin gate oxide is described. The nitrogen enrichment increases the dielectric constant of the gate oxide thereby decreasing it's effective oxide thickness. This in turn enhances the performance of MOSFET devices formed thereon. The nitrogen enrichment is accomplished by first enriching the surface of a silicon wafer with nitrogen by implanting nitrogen atoms into the silicon through a sacrificial screen oxide. After fixing the nitrogen by annealing, a nitrogen enriched gate oxide is thermally grown. Additional nitrogen is then infused into the gate oxide by remote plasma nitridation. This two step nitrogen enrichment process increases the dielectric constant of the gate oxide by a significant amount, approaching that of silicon nitride which not only decreases it's effective thickness with respect to gate capacitance, but also lowers device leakage by suppressing hot carrier injection over device drain regions.

Abstract: A method for making an improved ultra-thin silicon nitride-oxide gate insulating layer for field effect transistors (FETs) is achieved. After forming a field oxide to electrically isolate device areas on a silicon substrate, an ultra-thin silicon nitride-oxide insulating layer is formed in two process steps. In the first process step a silicon nitride layer is formed on the device areas on the substrate using a low-pressure rapid thermal process (LP-RTP) and a reactant gas of ammonia (NH3) while insuring that the RTP tool is free of oxygen. Then a second process step is carried out sequentially in the same LP-RTP at an elevated temperature and using an oxygen-rich ambient (dinitrogen oxide N2O) as a reoxidation gas. The non-self-limiting characteristic of the ultra-thin-silicon nitride layer results in the controllable diffusion of the dissociated oxygen (O) and nitrous oxide (NO) through the silicon nitride layer to form a thin good quality silicon oxide layer on and in the substrate surface.

Abstract: A method for simultaneously annealing a source/drain region and removing an overlying native oxide layer using a H2 anneal in the fabrication of integrated circuits is described. Semiconductor device structures are provided in and on a semiconductor substrate wherein the semiconductor device structures include gate electrodes and associated source and drain regions. A resist protective dielectric layer is deposited overlying the semiconductor device structures. The resist protective dielectric layer is etched away where it is not covered by a mask exposing a top surface of the gate electrode and a surface of the semiconductor substrate overlying the source and drain regions wherein a native oxide layer forms on the exposed surfaces. The substrate is annealed using H2 whereby the native oxide is removed and whereby the exposed surface of the semiconductor substrate is recrystallized.

Abstract: A new method of pre-oxidation cleaning of a substrate surface is described. The surface of a semiconductor substrate of a wafer is cleaned using a multiple step cleaning process wherein the final step of the cleaning process comprises cleaning with a solution of H2SO4 and H2O2 whereby a chemical oxide initial layer is formed on the surface of the wafer. Thereafter, the surface of the wafer is oxidized to form a thermal oxide layer wherein the chemical oxide layer and the thermal oxide layer together form a gate oxide layer in the fabrication of an integrated circuit.

Abstract: A method is disclosed to form a plurality of oxides of different thicknesses with one step oxidation. In a first embodiment, a substrate is provided having a high-voltage cell area and a peripheral low-voltage logic area separated by a trench isolation region. The substrate is first nitrided. Then the nitride layer over the high-voltage area is removed, and the substrate is wet cleaned with HF solution. The substrate surface is next oxidized to form a tunnel oxide of desired thickness over the high-voltage. In a second embodiment, a sacrificial oxide is used over the substrate for patterning the high voltage cell area and the low-voltage logic area. The sacrificial oxide is removed from the low-voltage area and the substrate is nitrided after cleaning with a solution not containing HF, thus forming a nitride layer over the low-voltage area. Then, the sacrificial oxide is removed from the high-voltage area with an HF dip, and tunnel oxide of desired thickness is formed over the same area.

Abstract: A new method is provided to anneal the gate oxide after the gate oxide has been grown. The first embodiment of the invention teaches a two step anneal, a first anneal using H2 followed by a second anneal using N2. The second embodiment of the invention teaches a one step anneal using H2 mixed with N2. The third embodiment of the invention teaches a one step anneal using pure H2.

Abstract: A process for forming an ultra-thin, silicon dioxide, gate insulator layer, for narrow channel length MOSFET devices, has been developed. The process features the use of a two step, in situ steam generated, (ISSG), procedure, to grow a silicon dioxide layer at a physical thickness between about 10 to 20 Angstroms, offering a gate insulator layer with a reduction in leakage current, during standby, or operating modes, when compared to counterpart silicon dioxide layers, formed without the use of the two step, ISSG procedure. The two step, ISSG procedure is comprised of a first step, featuring a steam oxidation, and an in situ anneal, in a nitrous oxide ambient, followed by the second step of the two step, ISSG procedure, performed in situ, in the same furnace used for the first step of the two step, ISSG procedure, with the second step of the two step, ISSG procedure again comprised of a steam oxidation, followed by an in situ anneal, performed in a nitrous oxide ambient.

Abstract: A new method is provided for introducing nitrogen concentrations into oxide layers. The first embodiment of the invention teaches a NO/N2O pre-oxidation anneal followed by a re-oxidation followed by a NO/N2O/NH3 anneal. The second embodiment of the invention teaches the formation of a layer of sacrificial oxide, followed by a nitrogen implantation followed by the removal of the sacrificial oxide followed by the gate oxide formation followed by a NO/N2O/NH3 anneal.

Abstract: A process for significantly reducing the thickness of and improving the quality and uniformity of a native oxide film which is formed during the formation of MOSFET devices on a silicon wafer in a dual thickness gate oxide process. The native oxide forms on exposed silicon surfaces after selectively etching away regions of a first thicker gate oxide and prior to growing a thinner gate oxide. The thinner gate oxide used to form high performance devices is between about 15 and 50 Å thick. The native oxide which forms on the exposed silicon surfaces has an initial thickness of about 10 Å. After the selective regions have been patterned the wafer is cleaned using a totally HF free cleaning procedure and subjected to a low pressure rapid thermal annealing between about 600 and 1,050° C. in an ambient of H2 and N2. The residual oxide thickness is reduced to about 4 Å with an accompanying improvement in thickness uniformity and oxide quality.

Abstract: A new method of using a NO or N.sub.2 O treatment on a first area on a wafer in order to form a thinner oxide film in the first area and a thicker oxide film in a second area on a wafer using a single oxidation step is achieved. A semiconductor substrate of a silicon wafer is provided wherein a first area is separated from a second area by an isolation region. The silicon substrate in the second area is treated with NO or N.sub.2 O whereby a high-nitrogen silicon oxide layer is formed on the surface of semiconductor substrate in the second area. A tunnel window is defined in the first area and the oxide layer within the tunnel window is removed. The silicon wafer is oxidized whereby a tunnel oxide layer forms within the tunnel window and whereby a gate oxide layer is formed overlying the high-nitrogen silicon oxide layer in the second area. The tunnel oxide layer has a greater thickness than the combined thickness of the gate oxide layer and the high-nitrogen silicon oxide layer.