Abstract: A method of detecting L-shaped target objects within a point cloud includes rotating a target point cloud through a plurality of rotation angles and generating at least one weighted histogram for each of the plurality of rotation angles, wherein the weighted histogram includes a first plurality of bins, each bin having a width defined in a first axis, wherein each bin is weighted based on a number of points located within the bin and a distance between points in a direction perpendicular to a width of the bin. A score is generated for each of the plurality of rotation angles based on the at least one weighted histogram and determining whether a target point cloud is L-shaped based on the generated scores.

Abstract: A heat dissipation system of a portable electronic device including a first processing element, a second processing element, a heat dissipation module located between the first processing element and the second processing element, a first heat transferring member, and a second heat transferring member, is provided. The first processing element has a first region and a second region. The first heat transferring member is in thermal contact with the first region, the second processing element, and the heat dissipation module. The second heat transferring member is in thermal contact with the second region and the heat dissipation module.

Abstract: A transistor includes a III-N channel layer; a III-N barrier layer on the III-N channel layer; a source contact and a drain contact, the source and drain contacts electrically coupled to the III-N channel layer; an insulator layer on the III-N barrier layer; a gate insulator partially on the insulator layer and partially on the III-N channel layer, the gate insulator including an amorphous Al1-xSixO layer with 0.2<x<0.8; and a gate electrode over the gate insulator, the gate electrode being positioned between the source and drain contacts.

Abstract: A semiconductor structure includes a semiconductor device, a conductive line, a dielectric layer and a redistribution layer (RDL). The conductive line is present over the semiconductor device. The dielectric layer is present over the conductive line. The RDL includes a conductive structure over the dielectric layer and a conductive via extending downwards from the conductive structure and through the dielectric layer. The conductive via comprises a bottom portion, a top portion, and a tapered portion between the bottom and top portions, wherein the tapered portion has a width variation greater than that of the bottom and top portions.

Abstract: A method of forming a semiconductor structure includes the following steps. A dielectric layer is formed over a conductive line. A photoresist layer is formed over the dielectric layer. The photoresist layer is patterned to form a mask feature and an opening is defined by the mask feature. The opening has a bottom portion and a top portion communicated to the bottom portion, and the top portion is wider than the bottom portion. The dielectric layer is etched to form a via hole in the dielectric layer using the mask feature as an etch mask, such that the via hole has a bottom portion and a tapered portion over the bottom portion. The conductive material is filled in the via hole to form a conductive via.

Abstract: A method of detecting L-shaped target objects within a point cloud includes rotating a target point cloud through a plurality of rotation angles and generating at least one weighted histogram for each of the plurality of rotation angles, wherein the weighted histogram includes a first plurality of bins, each bin having a width defined in a first axis, wherein each bin is weighted based on a number of points located within the bin and a distance between points in a direction perpendicular to a width of the bin. A score is generated for each of the plurality of rotation angles based on the at least one weighted histogram and determining whether a target point cloud is L-shaped based on the generated scores.

Abstract: A transistor includes a III-N channel layer; a III-N barrier layer on the III-N channel layer; a source contact and a drain contact, the source and drain contacts electrically coupled to the III-N channel layer; an insulator layer on the III-N barrier layer; a gate insulator partially on the insulator layer and partially on the III-N channel layer, the gate insulator including an amorphous Al1-xSixO layer with 0.2<x<0.8; and a gate electrode over the gate insulator, the gate electrode being positioned between the source and drain contacts.

Abstract: A method of forming a semiconductor structure includes the following steps. A dielectric layer is formed over a conductive line. A photoresist layer is formed over the dielectric layer. The photoresist layer is patterned to form a mask feature and an opening is defined by the mask feature. The opening has a bottom portion and a top portion communicated to the bottom portion, and the top portion is wider than the bottom portion. The dielectric layer is etched to form a via hole in the dielectric layer using the mask feature as an etch mask, such that the via hole has a bottom portion and a tapered portion over the bottom portion. The conductive material is filled in the via hole to form a conductive via.

Abstract: The present disclosure provides an interconnect structure. The interconnect structure includes a first connecting line, a second connecting line disposed over the first connecting line, and a connecting via disposed in a dielectric structure between the first connecting line and the second connecting line, and electrically connecting the first connecting line and the second connecting line. The connecting via includes a head portion and a body portion, and a width of the head portion is greater than a width of the body portion.

Abstract: The present disclosure provides a method for preparing an interconnect structure. One aspect of the present disclosure provides a method for preparing an interconnect structure. The method includes the following steps. A first dielectric layer is provided over a first connecting line. A first upper via opening is formed in the first dielectric layer, wherein the first upper via opening has a first width. A first lower via opening is formed in the first dielectric layer, wherein the first lower via opening is formed under and coupled to the first upper via opening. The first lower via opening has a second width less than the first width of the first upper via opening. A connecting via is formed in the first upper via opening and the first lower via opening. A second connecting line is formed over the connecting via.

Abstract: The present disclosure provides an electronic device and a method of manufacturing the same. The electronic device includes a multilayer component, at least one contact pad, a passivation layer, a dielectric layer, and a metallic layer. The contact pad is disposed on the multilayer component, the passivation layer covers the multilayer component and the contact pad, and the dielectric layer is disposed on the passivation layer. The metallic layer penetrates through the dielectric layer and the passivation layer and is connected to the contact pad, and the metallic layer discretely tapers at positions of decreasing distance from the contact pad.

Abstract: A method of fabricating a III-N device includes forming a III-N channel layer on a substrate, a III-N barrier layer on the channel layer, an insulator layer on the barrier layer, and a trench in a first portion of the device. Forming the trench comprises removing the insulator layer and a part of the barrier layer in the first portion of the device, such that a remaining portion of the barrier layer in the first portion of the device has a thickness away from a top surface of the channel layer, the thickness being within a predetermined thickness range, annealing the III-N device in a gas ambient including oxygen at an elevated temperature to oxidize the remaining portion of the barrier layer in the first portion of the device, and removing the oxidized remaining portion of the barrier layer in the first portion of the device.

Abstract: The invention provides a semiconductor device including a substrate, a dielectric layer, a dummy bonding pad, a bonding pad, a redistribution layer, and a metal interconnect. The substrate includes a non-device region and a device region. The dielectric layer is on the non-device region and the device region. The dummy bonding pad is on the dielectric layer of the non-device region. The metal interconnect is in the dielectric layer of the non-device region and connected to the dummy bonding pad. The bonding pad is on the dielectric layer of the device region. The buffer layer is between the bonding pad and the dielectric layer. The buffer layer includes metal, metal nitride, or a combination thereof. The redistribution layer is on the dielectric layer and connects the dummy bonding pad and the bonding pad.

Abstract: The invention provides a semiconductor device including a substrate, a dielectric layer, a dummy bonding pad, a bonding pad, a redistribution layer, and a metal interconnect. The substrate includes a non-device region and a device region. The dielectric layer is on the non-device region and the device region. The dummy bonding pad is on the dielectric layer of the non-device region. The metal interconnect is in the dielectric layer of the non-device region and connected to the dummy bonding pad. The bonding pad is on the dielectric layer of the device region. The buffer layer is between the bonding pad and the dielectric layer. The buffer layer includes metal, metal nitride, or a combination thereof. The redistribution layer is on the dielectric layer and connects the dummy bonding pad and the bonding pad.

Abstract: The invention provides a semiconductor device including a substrate, a dielectric layer, a dummy bonding pad, a bonding pad, a redistribution layer, and a metal interconnect. The substrate includes a non-device region and a device region. The dielectric layer is on the non-device region and the device region. The dummy bonding pad is on the dielectric layer of the non-device region. The metal interconnect is in the dielectric layer of the non-device region and connected to the dummy bonding pad. The bonding pad is on the dielectric layer of the device region. The buffer layer is between the bonding pad and the dielectric layer. The buffer layer includes metal, metal nitride, or a combination thereof. The redistribution layer is on the dielectric layer and connects the dummy bonding pad and the bonding pad.

Abstract: A method of fabricating a III-N device includes forming a III-N channel layer on a substrate, a III-N barrier layer on the channel layer, an insulator layer on the barrier layer, and a trench in a first portion of the device. Forming the trench comprises removing the insulator layer and a part of the barrier layer in the first portion of the device, such that a remaining portion of the barrier layer in the first portion of the device has a thickness away from a top surface of the channel layer, the thickness being within a predetermined thickness range, annealing the III-N device in a gas ambient including oxygen at an elevated temperature to oxidize the remaining portion of the barrier layer in the first portion of the device, and removing the oxidized remaining portion of the barrier layer in the first portion of the device.

Abstract: A method of fabricating a III-N device includes forming a III-N channel layer on a substrate, a III-N barrier layer on the channel layer, an insulator layer on the barrier layer, and a trench in a first portion of the device. Forming the trench comprises removing the insulator layer and a part of the barrier layer in the first portion of the device, such that a remaining portion of the barrier layer in the first portion of the device has a thickness away from a top surface of the channel layer, the thickness being within a predetermined thickness range, annealing the III-N device in a gas ambient including oxygen at an elevated temperature to oxidize the remaining portion of the barrier layer in the first portion of the device, and removing the oxidized remaining portion of the barrier layer in the first portion of the device.

Abstract: A method of fabricating a III-N device includes forming a III-N channel layer on a substrate, a III-N barrier layer on the channel layer, an insulator layer on the barrier layer, and a trench in a first portion of the device. Forming the trench comprises removing the insulator layer and a part of the barrier layer in the first portion of the device, such that a remaining portion of the barrier layer in the first portion of the device has a thickness away from a top surface of the channel layer, the thickness being within a predetermined thickness range, annealing the III-N device in a gas ambient including oxygen at an elevated temperature to oxidize the remaining portion of the barrier layer in the first portion of the device, and removing the oxidized remaining portion of the barrier layer in the first portion of the device.

Abstract: The invention provides a semiconductor device including a substrate, a dielectric layer, a dummy bonding pad, a bonding pad, a redistribution layer, and a metal interconnect. The substrate includes a non-device region and a device region. The dielectric layer is on the non-device region and the device region. The dummy bonding pad is on the dielectric layer of the non-device region. The metal interconnect is in the dielectric layer of the non-device region and connected to the dummy bonding pad. The bonding pad is on the dielectric layer of the device region. The buffer layer is between the bonding pad and the dielectric layer. The buffer layer includes metal, metal nitride, or a combination thereof The redistribution layer is on the dielectric layer and connects the dummy bonding pad and the bonding pad.

Abstract: The present invention, which enables to align a liquid crystal molecule, when no voltage is applied thereto, and also to control pretilt angle of the liquid crystal molecule, relates to a composition for a liquid crystal alignment film comprising components represented by the following (A) to (D): (A) a meta-phenylene diamine derivative represented by the general formula [1]; (B) a meta-phenylene diamine derivative represented by the general formula [2]; (C) a para-arylene diamine represented by the general formula [3]; (D) a tetracarboxylic acid represented by the general formula [4] or a tetracarboxylic acid anhydride represented by the general formula [4?]; (wherein R1 represents an alkyl group having 1 to 6 carbon atoms or the like, R2 represents an alkyl group having 8 to 20 carbon atoms or the like, t moieties of Ra represent an alkyl group having 1 to 3 carbon atoms or the like, n represents an integer of 1 to 3, t represents an integer of 0 to 4, T represents an oxygen atom or the like, Y repre