Abstract: Latch-up of CMOS devices is improved by using a structure having electrically coupled but floating doped regions between the N-channel and P-channel devices. The doped regions desirably lie substantially parallel to the source-drain regions of the devices between the Pwell and Nwell regions in which the source-drain regions are located. A first (“N BAR”) doped region forms a PN junction with the Pwell, spaced apart from a source/drain region in the Pwell, and a second (“P BAR”) doped region forms a PN junction with the Nwell, spaced apart from a source/drain region in the Nwell. A further NP junction lies between the N BAR and P BAR regions. The N BAR and P BAR regions are ohmically coupled, preferably by a low resistance metal conductor, and otherwise floating with respect to the device or circuit reference potentials (e.g., Vss, Vdd).

Abstract: Latch-up of CMOS devices (20, 20?) is improved by using a structure (40, 40?, 80) having electrically coupled but floating doped regions (64, 64?; 65, 65?) between the N-channel (44) and P-channel (45) devices. The doped regions (64, 64?; 65, 65?) desirably lie substantially parallel to the source-drain regions (422, 423; 432, 433) of the devices (44, 45) between the Pwell (42) and Nwell (43) regions in which the source-drain regions (422, 423; 432, 433) are located. A first (“N BAR”) doped region (64, 64?) forms a PN junction (512) with the Pwell (42), spaced apart from a source/drain region (423) in the Pwell (42), and a second (“P BAR”) doped region (55, 55?) forms a PN junction (513) with the Nwell (43), spaced apart from a source/drain region (433) in the Nwell (43). A further NP junction (511) lies between the N BAR (64) and P BAR (65) regions.

Abstract: Latch-up of CMOS devices (20, 20?) is improved by using a structure (40, 40?, 80) having electrically coupled but floating doped regions (64, 64?; 65, 65?) between the N-channel (44) and P-channel (45) devices. The doped regions (64, 64?; 65, 65?) desirably lie substantially parallel to the source-drain regions (422, 423; 432, 433) of the devices (44, 45) between the Pwell (42) and Nwell (43) regions in which the source-drain regions (422, 423; 432, 433) are located. A first (“N BAR”) doped region (64, 64?) forms a PN junction (512) with the Pwell (42), spaced apart from a source/drain region (423) in the Pwell (42), and a second (“P BAR”) doped region (55, 55?) forms a PN junction (513) with the Nwell (43), spaced apart from a source/drain region (433) in the Nwell (43). A further NP junction (511) lies between the N BAR (64) and P BAR (65) regions.

Abstract: A tunable antifuse element (102, 202, 204, 504, 952) includes a substrate material (101) having an active area (106) formed in a surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a dielectric layer (110) disposed between the gate electrode (104) and the active area (106). The dielectric layer (110) includes a tunable stepped structure (127). During operation, a voltage applied between the gate electrode (104) and the active area (106) creates a current path through the dielectric layer (110) and a rupture of the dielectric layer (110) in a rupture region (130). The dielectric layer (110) is tunable by varying the stepped layer thicknesses and the geometry of the layer.

Abstract: A tunable antifuse element (102, 202, 204, 504, 952) includes a substrate material (101) having an active area (106) formed in a surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a dielectric layer (110) disposed between the gate electrode (104) and the active area (106). The dielectric layer (110) includes a tunable stepped structure (127). During operation, a voltage applied between the gate electrode (104) and the active area (106) creates a current path through the dielectric layer (110) and a rupture of the dielectric layer (110) in a rupture region (130). The dielectric layer (110) is tunable by varying the stepped layer thicknesses and the geometry of the layer.

Abstract: A tunable antifuse element (102, 202, 204, 504, 952) and method of fabricating the tunable antifuse element, including a substrate material (101) having an active area (106) formed in a surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a dielectric layer (110) disposed between the gate electrode (104) and the active area (106). The dielectric layer (110) including the fabrication of one of a tunable stepped structure (127). During operation, a voltage applied between the gate electrode (104) and the active area (106) creates a current path through the dielectric layer (110) and a rupture of the dielectric layer (110) in a plurality of rupture regions (130). The dielectric layer (110) is tunable by varying the stepped layer thicknesses and the geometry of the layer.

Abstract: Methods and apparatus are provided for a MOSFET (50, 99, 199) exhibiting increased source-drain breakdown voltage (BVdss). Source (S) (70) and drain (D) (76) are spaced apart by a channel (90) underlying a gate (84) and one or more carrier drift spaces (92, 92?) serially located between the channel (90) and the source (70, 70?) or drain (76, 76?). A buried region (96, 96?) of the same conductivity type as the drift space (92, 92?) and the source (70, 70?) or drain (76, 76?) is provided below the drift space (92, 92?), separated therefrom in depth by a narrow gap (94, 94?) and ohmically coupled to the source (70, 70?) or drain (76, 76?). Current flow (110) through the drift space produces a potential difference (Vt) across this gap (94, 94?).

Abstract: Methods and apparatus are provided for a MOSFET (50, 99, 199) exhibiting increased source-drain breakdown voltage (BVdss). Source (S) (70) and drain (D) (76) are spaced apart by a channel (90) underlying a gate (84) and one or more carrier drift spaces (92, 92?) serially located between the channel (90) and the source (70, 70?) or drain (76, 76?). A buried region (96, 96?) of the same conductivity type as the drift space (92, 92?) and the source (70, 70?) or drain (76, 76?) is provided below the drift space (92, 92?), separated therefrom in depth by a narrow gap (94, 94?) and ohmically coupled to the source (70, 70?) or drain (76, 76?). Current flow (110) through the drift space produces a potential difference (Vt) across this gap (94, 94?).

Abstract: Methods and apparatus are provided for a MOSFET (50, 99, 199) exhibiting increased source-drain breakdown voltage (BVdss). Source (S) (70) and drain (D) (76) are spaced apart by a channel (90) underlying a gate (84) and one or more carrier drift spaces (92, 92?) serially located between the channel (90) and the source (70, 70?) or drain (76, 76?). A buried region (96, 96?) of the same conductivity type as the drift space (92, 92?) and the source (70, 70?) or drain (76, 76?) is provided below the drift space (92, 92?), separated therefrom in depth by a narrow gap (94, 94?) and ohmically coupled to the source (70, 70?) or drain (76, 76?). Current flow (110) through the drift space produces a potential difference (Vt) across this gap (94, 94?).

Abstract: A tunable antifuse element (102, 202, 204, 504, 952) and method of fabricating the tunable antifuse element, including a substrate material (101) having an active area (106) formed in a surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a dielectric layer (110) disposed between the gate electrode (104) and the active area (106). The dielectric layer (110) including the fabrication of one of a tunable stepped structure (127). During operation, a voltage applied between the gate electrode (104) and the active area (106) creates a current path through the dielectric layer (110) and a rupture of the dielectric layer (110) in a plurality of rupture regions (130). The dielectric layer (110) is tunable by varying the stepped layer thicknesses and the geometry of the layer.

Abstract: Methods and apparatus are provided for a MOSFET (50, 99, 199) exhibiting increased source-drain breakdown voltage (BVdss). Source (S) (70) and drain (D) (76) are spaced apart by a channel (90) underlying a gate (84) and one or more carrier drift spaces (92, 92?) serially located between the channel (90) and the source (70, 70?) or drain (76, 76?). A buried region (96, 96?) of the same conductivity type as the drift space (92, 92?) and the source (70, 70?) or drain (76, 76?) is provided below the drift space (92, 92?), separated therefrom in depth by a narrow gap (94, 94?) and ohmically coupled to the source (70, 70?) or drain (76, 76?). Current flow (110) through the drift space produces a potential difference (Vt) across this gap (94, 94?).

Abstract: A Bipolar Junction Transistor (BJT) that reduces the variation in the current gain through the use of a trench pullback structure. The trench pullback structure is comprised of a trench and an active region. The trench reduces recombination in the emitter-base region through increasing the distance charge carriers must travel between the emitter and the base. The trench also reduces recombination by reducing the amount of interfacial traps that the electrons injected from the emitter are exposed to. Further, the trench is pulled back from the emitter allowing an active region where electrons injected from a sidewall of the emitter can contribute to the overall injected emitter current. This structure offers the same current capability and current gain as a device without the trench between the emitter and the base while reducing the current gain variation.

Abstract: A structure protects CMOS logic from substrate minority carrier injection caused by the inductive switching of a power device. A single Integrated Circuit (IC) supports one or more power MOSFETs and one or more arrays of CMOS logic. A highly doped ring is formed between the drain of the power MOSFET and the CMOS logic array to provide a low resistance path to ground for the injected minority carriers. Under the CMOS logic is a highly doped buried layer to form a region of high recombination for the injected minority carriers. One or more CMOS devices are formed above the buried layer. The substrate is a resistive and the injected current is attenuated. The well in which the CMOS devices rest forms a low resistance ground plane for the injected minority carriers.

Abstract: A structure protects CMOS logic from substrate minority carrier injection caused by the inductive switching of a power device. A single Integrated Circuit (IC) supports one or more power MOSFETs and one or more arrays of CMOS logic. A highly doped ring is formed between the drain of the power MOSFET and the CMOS logic array to provide a low resistance path to ground for the injected minority carriers. Under the CMOS logic is a highly doped buried layer to form a region of high recombination for the injected minority carriers. One or more CMOS devices are formed above the buried layer. The substrate is a resistive and the injected current is attenuated. The well in which the CMOS devices rest forms a low resistance ground plane for the injected minority carriers.

Abstract: A Bipolar Junction Transistor (BJT) that reduces the variation in the current gain through the use of a trench pullback structure. The trench pullback structure is comprised of a trench and an active region. The trench reduces recombination in the emitter-base region through increasing the distance charge carriers must travel between the emitter and the base. The trench also reduces recombination by reducing the amount of interfacial traps that the electrons injected from the emitter are exposed to. Further, the trench is pulled back from the emitter allowing an active region where electrons injected from a sidewall of the emitter can contribute to the overall injected emitter current. This structure offers the same current capability and current gain as a device without the trench between the emitter and the base while reducing the current gain variation.