Abstract: A layer transfer technique in which a portion of a donor wafer is doped with positively charged hydrogen ions and positively charged helium ions before it is bonded to a portion of a handle wafer. Furthermore, the bonded wafers are annealed at one of two annealing temperatures, which determines whether the wafers are separated using a thermal cleave or a mechanical cleave process.

Abstract: In one embodiment, a method comprises placing a first and a second substrate into a reaction chamber, the first substrate being made of an indium antimonide material and having a first surface and the second substrate being made of a silicon or a silicon dioxide material and having a second surface; exposing the first and second surfaces to an oxygen plasma; forming a bond between the first and the second substrates by placing the first surface in contact with the second surface; and annealing the first and the second substrates to strengthen the bond.

Abstract: Embodiments of the invention provide substrate with an insulator layer on the substrate. The insulator layer may comprise diamond-like carbon. A device, such a tri-gate transistor may be formed on the diamond-like carbon layer.

Abstract: A method and article to provide a three-dimensional (3-D) IC wafer process flow. In some embodiments, the method and article include bonding a device layer of a multilayer wafer to a device layer of another multilayer wafer to form a bonded pair of device layers, each of the multilayer wafers including a layer of silicon on a layer of porous silicon (SiOPSi) on a silicon substrate where the device layer is formed in the silicon layer, separating the bonded pair of device layers from one of the silicon substrates by splitting one of the porous silicon layers, and separating the bonded pair of device layers from the remaining silicon substrate by splitting the other one of the porous silicon layers to provide a vertically stacked wafer.

Abstract: Arrangements incorporating laser-induced cleaving.

Abstract: Embodiments of a silicon-on-insulator (SOI) wafer having an etch stop layer overlying the buried oxide layer, as well as embodiments of a method of making the same, are disclosed. The etch stop layer may comprise silicon nitride, nitrogen-doped silicon dioxide, or silicon oxynitride, as well as some combination of these materials. Other embodiments are described and claimed.

Abstract: A high mobility semiconductor assembly. In one exemplary aspect, the high mobility semiconductor assembly includes a first substrate having a first reference orientation located at a <110> crystal plane location on the first substrate and a second substrate formed on top of the first substrate. The second substrate has a second reference orientation located at a <100> crystal plane location on the second substrate, wherein the first reference orientation is aligned with the second reference orientation. In another exemplary aspect, the second substrate has a second reference orientation located at a <110> crystal plane location on the second substrate, wherein the second substrate is formed over the first substrate with the second reference orientation being offset to the first reference orientation by about 45 degrees.

Abstract: Methods of forming a germanium on insulator structure and its associated structures are described. Those methods comprise forming an epitaxial germanium layer on a sacrificial silicon layer, removing a portion of the epitaxial germanium layer, activating the epitaxial germanium layer and an oxide layer disposed on a silicon substrate in an oxygen plasma, and bonding the epitaxial germanium layer to the oxide layer to form a germanium on insulator structure.

Abstract: Methods of forming a germanium on insulator structure and its associated structures are described. Those methods comprise forming an epitaxial germanium layer on a sacrificial silicon layer, removing a portion of the epitaxial germanium layer, activating the epitaxial germanium layer and an oxide layer disposed on a silicon substrate in an oxygen plasma, and bonding the epitaxial germanium layer to the oxide layer to form a germanium on insulator structure.

Abstract: In one embodiment, a method comprises placing a first and a second substrate into a reaction chamber, the first substrate being made of an indium antimonide material and having a first surface and the second substrate being made of a silicon or a silicon dioxide material and having a second surface; exposing the first and second surfaces to an oxygen plasma; forming a bond between the first and the second substrates by placing the first surface in contact with the second surface; and annealing the first and the second substrates to strengthen the bond.

Abstract: An assembly comprising a semiconductor substrate having a first lattice constant, an intermediate layer having a second lattice constant formed on the semiconductor substrate, and a virtual substrate layer having a third lattice constant formed on the intermediate layer. The intermediate layer comprises one of a combination of III-V elements and a combination of II-VI elements. The second lattice constant has a value that is approximately between the values of the first lattice constant and the third lattice constant.

Abstract: A high mobility semiconductor assembly. In one exemplary aspect, the high mobility semiconductor assembly includes a first substrate having a first reference orientation located at a <110> crystal plane location on the first substrate and a second substrate formed on top of the first substrate. The second substrate has a second reference orientation located at a <100> crystal plane location on the second substrate, wherein the first reference orientation is aligned with the second reference orientation. In another exemplary aspect, the second substrate has a second reference orientation located at a <110> crystal plane location on the second substrate, wherein the second substrate is formed over the first substrate with the second reference orientation being offset to the first reference orientation by about 45 degrees.

Abstract: The crystal orientations of monocrystalline semiconductor wafers may be varied by four parameters. The first parameter is the type of crystal seed used to grow the monocrystalline semiconductor ingot from which the wafers are cut. The second parameter is the angle at which the wafer is sliced from the ingot. The third parameter is the crystal plane towards which the wafer is cut. And, the fourth parameter is the position of the orientation indication feature that is used to align the wafer during processing. Different combinations of these parameters provide variations of non-standard crystal orientations of monocrystalline semiconductor wafers and semiconductor-on-insulator substrates such as silicon-on-insulator.

Abstract: The invention provides a strained silicon layer with a reduced roughness. Reduced cross-hatching in the strained silicon layer may allow the reduced roughness.

Abstract: More complete bonding of wafers may be achieved out to the edge regions of the wafer by constrained bond strengthening of the wafers in a pressure bonding apparatus after direct wafer bonding. The pressure bonding process may be accompanied by the application of not above room temperature.

Abstract: A method is provided for fabricating an SOI water. This may involve forming a silicon substrate and implanting oxygen into the substrate. Damaged portions of the implanted silicon may be healed/cured by CMP or anneal, for example. An epi layer may then be deposited over the healed/cured regions of the substrate. The substrate may then be annealed to form an insulative layer. The wafer may be thinned to provide the proper thickness of the epi layer.

Abstract: More complete bonding of wafers may be achieved out to the edge regions of the wafer by constrained bond strengthening of the wafers in a pressure bonding apparatus after direct wafer bonding. The pressure bonding process may be accompanied by the application of not above room temperature.

Abstract: Embodiments of the present invention propose a bulk heat dissipation substrate that is part of the substrate on which the devices of an integrated circuit are formed. The bulk layer is formed directly under the device layer of a semiconductor substrate and has a thermal conductivity greater than that of the semiconductor substrate. It is a simple passive technique for the removal of heat during device operation. It is also very effective at the removal of heat from hot spots, or areas of excessive heat, because the heat dissipation material is in direct contact with the substrate on which the devices are formed. Such a material is also valuable for the dissipation of heat during the processing of the wafer substrate because it can be coupled to the semiconductor wafer before processing.

Abstract: Methods of forming a germanium on insulator structure and its associated structures are described. Those methods comprise forming an epitaxial germanium layer on a sacrificial silicon layer, removing a portion of the epitaxial germanium layer, activating the epitaxial germanium layer and an oxide layer disposed on a silicon substrate in an oxygen plasma, and bonding the epitaxial germanium layer to the oxide layer to form a germanium on insulator structure.

Abstract: A method for in situ formation of low defect, strained silicon and a device formed according to the method are disclosed. In one embodiment, a silicon germanium layer is formed on a substrate, and a portion of the silicon germanium layer is removed to expose a surface that is smoothed with a smoothing agent. A layer of strained silicon is formed on the silicon germanium layer. In various embodiments, the entire method is conducted in a single processing chamber, which is kept under vacuum.