Abstract: The present disclosure provides a method of fabricating a sensor assembly in which a sensor surface has an anchor species provided thereon, the anchor species having a first functional group attached. The method further comprises disposing a fluid channel over the surface and subsequently providing an analyte capture species to the fluid channel. The analyte capture species comprises a second functional group configured to react with the first functional group. The surface is then exposed to photo radiation and the first and second functional groups react forming a link between the analyte capture species and the anchor species on the sensing surface.

Abstract: The present disclosure provides a method of fabricating a target capture and sensor assembly. The method comprises the steps of: providing a fluid path with a target capture surface comprising an anchor species with a first functional group disposed thereon; providing a target capture species to the target capture surface of the fluid path, wherein each target capture species comprises a target capture part and a second functional group configured to react with the first functional group; and exposing at least a portion of the target capture surface of the fluid path to photo radiation so as to cause a photo-initiated reaction between the first functional group and the second functional group, wherein the target capture and sensor assembly further comprises a sensing surface in the fluid path and wherein the target capture surface and the sensing surface are in fluid communication with one another.

Abstract: A sensing assembly comprises for detecting a property of a sample comprises a field effect transistor (FET) configured to output a first signal indicative of a property of a sample comprises: a first layer providing a sensing surface; a channel provided below the first layer; and a drain and a source in electrical communication with the channel. The sensing assembly may further comprise a gate provided below the first layer and the first layer comprises a one-dimensional or two-dimensional material. Alternatively or additionally, the first layer comprises N-polar hexagonal boron nitride (hBN).

Abstract: Provided are methods of manufacturing comprising providing a FET base structure, the FET base structure comprising a substrate, a drain and a source; and providing a channel layer on the FET base structure; and providing a first layer on the FET base structure. The first layer comprises a one-dimensional or two-dimensional material and is arranged on an upper surface of the channel layer so as to form a sensing surface of the FET. The step of providing the channel layer comprises forming the channel layer and subsequently transferring the channel layer onto the FET base structure. Alternatively or additionally, the step of providing the first layer on the FET base structure comprises forming the first layer and subsequently transferring the first layer onto the FET base structure.

Abstract: The present disclosure provides a reference electrode for providing a reference potential during measurement of a property of a sample. The reference electrode comprising: a reference electrode layer; and a reference layer provided over at least a part of the reference electrode layer and defining a sample receiving region which is separated from the reference electrode layer by the reference layer. In one embodiment, the reference layer comprises fluorinated or silanized graphene and/or fluorinated or silanized graphene oxide. Alternatively, the graphene or graphene oxide are functionalised or doped so as to form a super-hydrophobic reference layer.

Abstract: Sensors having dimensions on the order of nanometers can be arranged in an array. The sensors can detect substances found in an environment. The array of sensors can be disposed on a substrate along with circuitry to control the operation of the array of sensors.

Abstract: An inexpensive IR photodetector assembly that can provide high performance in SWIR applications, such as LIDAR. The photodetector assembly can operate as a photodiode, a phototransistor, or can include both a photodiode and a phototransistor. The hybrid photodetector can be composed of one or more absorber layer materials from a first semiconductor family, e.g., p-type InGaAs, laying on one or more wide-band gap semiconductor transducer layer materials from a second semiconductor family, e.g., aluminum gallium nitride (AlGaN) and gallium nitride (GaN), or AlGaN/n-GaN. As such, the absorber layer material and the wide band gap materials can be from two different semiconductor families, making the IR photodetector a hybrid of semiconductor families. After shining IR light onto the absorber layer material, the photo-generated electron-hole pairs can be collected as photocurrent in the photo-voltaic mode.

Abstract: Techniques to use energy band gap engineering (or band offset engineering) to produce a photodetector semiconductor assembly that can be tuned to absorb light in one or more wavelengths. For example, the assembly can be tuned to receive infrared (IR) and/or ultraviolet (UV) light. The photodetector assembly can operate as a photodiode, a phototransistor, or can include both a photodiode and a phototransistor.

Abstract: Low-cost and high-efficiency monolithically integrated nanoscale-based light emitter techniques can be used in, for example, electronic display applications and spectroscopy applications using spectrometers. Using various techniques, a light emitter can include quantum dots (QDs) and can be arranged to emit light in mono-band (e.g., one wavelength) or in broad-band (e.g., more than one wavelength) such as in the visible to mid-infrared range, e.g., from about 365 nm to about 10 ?m. The light emitter nanotechnology can be based on a nanoscale wafer manufacturing for displays and spectroscopy applications.

Abstract: Techniques to use energy band gap engineering (or band offset engineering) to produce a photodetector semiconductor assembly that can be tuned to absorb light in one or more wavelengths. For example, the assembly can be tuned to receive infrared (IR) and/or ultraviolet (UV) light. The photodetector assembly can operate as a photodiode, a phototransistor, or can include both a photodiode and a phototransistor.

Abstract: An inexpensive IR photodetector assembly that can provide high performance in SWIR applications, such as LIDAR. The photodetector assembly can operate as a photodiode, a phototransistor, or can include both a photodiode and a phototransistor. The hybrid photodetector can be composed of one or more absorber layer materials from a first semiconductor family, e.g., p-type InGaAs, laying on one or more wide-band gap semiconductor transducer layer materials from a second semiconductor family, e.g., aluminum gallium nitride (AlGaN) and gallium nitride (GaN), or AlGaN/n-GaN. As such, the absorber layer material and the wide band gap materials can be from two different semiconductor families, making the IR photodetector a hybrid of semiconductor families. After shining IR light onto the absorber layer material, the photo-generated electron-hole pairs can be collected as photocurrent in the photo-voltaic mode.

Abstract: Low-cost and high-efficiency monolithically integrated nanoscale-based light emitter techniques can be used in, for example, electronic display applications and spectroscopy applications using spectrometers. Using various techniques, a light emitter can include quantum dots (QDs) and can be arranged to emit light in mono-band (e.g., one wavelength) or in broad-band (e.g., more than one wavelength) such as in the visible to mid-infrared range, e.g., from about 365 nm to about 10 ?m. The light emitter nanotechnology can be based on a nanoscale wafer manufacturing for displays and spectroscopy applications.

Abstract: A semiconductor device such as a transistor includes a source region, a drain region, a semiconductor region, at least one island region and at least one gate region. The semiconductor region is located between the source region and the drain region. The island region is located in the semiconductor region. Each of the island regions differs from the semiconductor region in one or more characteristics selected from the group including resistivity, doping type, doping concentration, strain and material composition. The gate region is located between the source region and the drain region covering at least a portion of the island regions.

Abstract: Field-plate structures are disclosed for electrical field management in semiconductor devices. A field-plate semiconductor structure includes a semiconductor substrate, a source ohmic contact, a drain ohmic contact, and a gate contact disposed over a gate region between the source ohmic contact and the drain ohmic contact, and a source field plate connected to the source ohmic contact. A field-plate dielectric is disposed over the semiconductor substrate. An encapsulating dielectric is disposed over the gate contact, wherein the encapsulating dielectric covers a top surface of the gate contact. The source field plate is disposed over the field-plate dielectric in a field plate region, from which the encapsulating dielectric is absent.

Abstract: Field-plate structures are disclosed for electrical field management in semiconductor devices. A field-plate semiconductor structure includes a semiconductor substrate, a source ohmic contact, a drain ohmic contact, and a gate contact disposed over a gate region between the source ohmic contact and the drain ohmic contact, and a source field plate connected to the source ohmic contact. A field-plate dielectric is disposed over the semiconductor substrate. An encapsulating dielectric is disposed over the gate contact, wherein the encapsulating dielectric covers a top surface of the gate contact. The source field plate is disposed over the field-plate dielectric in a field plate region, from which the encapsulating dielectric is absent.

Abstract: A multi-layer semiconductor structure is disclosed for use in III-Nitride semiconductor devices, including a channel layer, a band-offset layer having a wider bandgap than the channel layer, a spacer layer having a narrower bandgap than the band-offset layer, and a cap layer comprising at least two sublayers. Each sublayer is selectively etchable with respect to sublayers immediately below and above, each sublayer comprises a III-N material AlxInyGazN in which 0?x?1, 0?y?1, and 0?z?1, at least one sublayer has a non-zero Ga content, and a sublayer immediately above the spacer layer has a wider bandgap than the spacer layer. Also described are methods for fabricating such semiconductor structures, with gate and/or ohmic recesses formed by selectively removing adjacent layers or sublayers. The performance of resulting devices is improved, while providing design flexibility to reduce production cost and circuit footprint.

Abstract: A semiconductor device includes a substrate, a first active layer, a second active layer, at least first and second electrodes, an E-field management layer, and at least one injection electrode. The first active layer is disposed over the substrate. The second active layer is disposed on the first active layer such that a laterally extending conductive channel arises which extends in a lateral direction. The laterally extending conductive channel is located between the first active layer and the second active layer. The first and second electrodes are electrically connected to the first active layer. The E-field management layer, which reduces the electric-field gradients arising in the first and second active layers, is disposed over the second active layer. The injection electrode is electrically connected to the E-field management layer.

Abstract: A multi-layer semiconductor structure is disclosed for use in III-Nitride semiconductor devices, including a channel layer, a band-offset layer having a wider bandgap than the channel layer, a spacer layer having a narrower bandgap than the band-offset layer, and a cap layer comprising at least two sublayers. Each sublayer is selectively etchable with respect to sublayers immediately below and above, each sublayer comprises a III-N material AlxInyGazN in which 0?x?1, 0?y?1, and 0?z?1, at least one sublayer has a non-zero Ga content, and a sublayer immediately above the spacer layer has a wider bandgap than the spacer layer. Also described are methods for fabricating such semiconductor structures, with gate and/or ohmic recesses formed by selectively removing adjacent layers or sublayers. The performance of resulting devices is improved, while providing design flexibility to reduce production cost and circuit footprint.

Abstract: Semiconductor structures are disclosed for monolithically integrating multiple III-N transistors with different threshold voltages on a common substrate. A semiconductor structure includes a cap layer comprising a plurality of selectively etchable sublayers, wherein each sublayer is selectively etchable with respect to the sublayer immediately below, wherein each sublayer comprises a material AlxInyGazN (0?x, y, z?1), and wherein at least one selectively etchable sublayer has a non-zero Ga content (0<z?1). A gate recess is disposed in a number of adjacent sublayers of the cap layer to achieve a desired threshold voltage for a transistor. Also described are methods for fabricating such semiconductor structures, where gate recesses and/or ohmic recesses are formed by selectively removing adjacent sublayers of the cap layer. The performance of the resulting integrated circuits is improved, while providing design flexibility to reduce production cost and circuit footprint.

Abstract: Semiconductor structures are disclosed for monolithically integrating multiple III-N transistors with different threshold voltages on a common substrate. A semiconductor structure includes a cap layer comprising a plurality of selectively etchable sublayers, wherein each sublayer is selectively etchable with respect to the sublayer immediately below, wherein each sublayer comprises a material AlxInyGazN (0?x, y, z?1), and wherein at least one selectively etchable sublayer has a non-zero Ga content (0<z?1). A gate recess is disposed in a number of adjacent sublayers of the cap layer to achieve a desired threshold voltage for a transistor. Also described are methods for fabricating such semiconductor structures, where gate recesses and/or ohmic recesses are formed by selectively removing adjacent sublayers of the cap layer. The performance of the resulting integrated circuits is improved, while providing design flexibility to reduce production cost and circuit footprint.