Patents by Inventor Mohamed Azize

Mohamed Azize has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160365437
    Abstract: A semiconductor device includes a substrate, a first active layer, a second active layer, at least first and second electrodes, an E-field management layer, and at least one injection electrode. The first active layer is disposed over the substrate. The second active layer is disposed on the first active layer such that a laterally extending conductive channel arises which extends in a lateral direction. The laterally extending conductive channel is located between the first active layer and the second active layer. The first and second electrodes are electrically connected to the first active layer. The E-field management layer, which reduces the electric-field gradients arising in the first and second active layers, is disposed over the second active layer. The injection electrode is electrically connected to the E-field management layer.
    Type: Application
    Filed: August 26, 2016
    Publication date: December 15, 2016
    Inventors: Bin Lu, Tomas Palacios, Ling Xia, Mohamed Azize
  • Publication number: 20160351564
    Abstract: A multi-layer semiconductor structure is disclosed for use in III-Nitride semiconductor devices, including a channel layer, a band-offset layer having a wider bandgap than the channel layer, a spacer layer having a narrower bandgap than the band-offset layer, and a cap layer comprising at least two sublayers. Each sublayer is selectively etchable with respect to sublayers immediately below and above, each sublayer comprises a III-N material AlxInyGazN in which 0?x?1, 0?y?1, and 0?z?1, at least one sublayer has a non-zero Ga content, and a sublayer immediately above the spacer layer has a wider bandgap than the spacer layer. Also described are methods for fabricating such semiconductor structures, with gate and/or ohmic recesses formed by selectively removing adjacent layers or sublayers. The performance of resulting devices is improved, while providing design flexibility to reduce production cost and circuit footprint.
    Type: Application
    Filed: August 11, 2016
    Publication date: December 1, 2016
    Inventors: Mohamed Azize, Bin Lu, Ling Xia
  • Patent number: 9502535
    Abstract: Semiconductor structures are disclosed for monolithically integrating multiple III-N transistors with different threshold voltages on a common substrate. A semiconductor structure includes a cap layer comprising a plurality of selectively etchable sublayers, wherein each sublayer is selectively etchable with respect to the sublayer immediately below, wherein each sublayer comprises a material AlxInyGazN (0?x, y, z?1), and wherein at least one selectively etchable sublayer has a non-zero Ga content (0<z?1). A gate recess is disposed in a number of adjacent sublayers of the cap layer to achieve a desired threshold voltage for a transistor. Also described are methods for fabricating such semiconductor structures, where gate recesses and/or ohmic recesses are formed by selectively removing adjacent sublayers of the cap layer. The performance of the resulting integrated circuits is improved, while providing design flexibility to reduce production cost and circuit footprint.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: November 22, 2016
    Assignee: Cambridge Electronics, Inc.
    Inventors: Ling Xia, Mohamed Azize, Bin Lu
  • Publication number: 20160300835
    Abstract: Semiconductor structures are disclosed for monolithically integrating multiple III-N transistors with different threshold voltages on a common substrate. A semiconductor structure includes a cap layer comprising a plurality of selectively etchable sublayers, wherein each sublayer is selectively etchable with respect to the sublayer immediately below, wherein each sublayer comprises a material AlxInyGazN (0?x, y, z?1), and wherein at least one selectively etchable sublayer has a non-zero Ga content (0<z?1). A gate recess is disposed in a number of adjacent sublayers of the cap layer to achieve a desired threshold voltage for a transistor. Also described are methods for fabricating such semiconductor structures, where gate recesses and/or ohmic recesses are formed by selectively removing adjacent sublayers of the cap layer. The performance of the resulting integrated circuits is improved, while providing design flexibility to reduce production cost and circuit footprint.
    Type: Application
    Filed: April 8, 2016
    Publication date: October 13, 2016
    Inventors: Ling Xia, Mohamed Azize, Bin Lu
  • Patent number: 9455342
    Abstract: A semiconductor device includes a substrate, a first active layer, a second active layer, at least first and second electrodes, an E-field management layer, and at least one injection electrode. The first active layer is disposed over the substrate. The second active layer is disposed on the first active layer such that a laterally extending conductive channel arises which extends in a lateral direction. The laterally extending conductive channel is located between the first active layer and the second active layer. The first and second electrodes are electrically connected to the first active layer. The E-field management layer, which reduces the electric-field gradients arising in the first and second active layers, is disposed over the second active layer. The injection electrode is electrically connected to the E-field management layer.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: September 27, 2016
    Assignee: CAMBRIDGE ELECTRONICS, INC.
    Inventors: Bin Lu, Tomas Palacios, Ling Xia, Mohamed Azize
  • Publication number: 20150349064
    Abstract: A semiconductor wafer includes a substrate and at least one nucleation layer overlying the substrate. The nucleation layer includes a AlxSiyCzNwOt composition with 0?x?1, 0?y?1, 0?z?1, 0?w?1, 0?t?1, and x×y>0 and with any additional impurities being less than 10% of the AlxSiyCzNwOt composition. The semiconductor wafer also includes a buffer layer structure overlying the nucleation layer. The buffer layer structure including at least one layer having a group III nitride composition.
    Type: Application
    Filed: May 5, 2015
    Publication date: December 3, 2015
    Inventors: Mohamed Azize, Ling Xia, Bin Lu, Tomas Palacios
  • Publication number: 20150349124
    Abstract: A semiconductor device such as a transistor includes a source region, a drain region, a semiconductor region, at least one island region and at least one gate region. The semiconductor region is located between the source region and the drain region. The island region is located in the semiconductor region. Each of the island regions differs from the semiconductor region in one or more characteristics selected from the group including resistivity, doping type, doping concentration, strain and material composition. The gate region is located between the source region and the drain region covering at least a portion of the island regions.
    Type: Application
    Filed: May 7, 2015
    Publication date: December 3, 2015
    Inventors: Bin Lu, Tomas Palacios, Ling Xia, Mohamed Azize
  • Publication number: 20150144957
    Abstract: A semiconductor device includes a substrate, a first active layer, a second active layer, at least first and second electrodes, an E-field management layer, and at least one injection electrode. The first active layer is disposed over the substrate. The second active layer is disposed on the first active layer such that a laterally extending conductive channel arises which extends in a lateral direction. The laterally extending conductive channel is located between the first active layer and the second active layer. The first and second electrodes are electrically connected to the first active layer. The E-field management layer, which reduces the electric-field gradients arising in the first and second active layers, is disposed over the second active layer. The injection electrode is electrically connected to the E-field management layer.
    Type: Application
    Filed: November 21, 2014
    Publication date: May 28, 2015
    Inventors: Bin Lu, Tomas Palacios, Ling Xia, Mohamed Azize