Patents by Inventor Mohamed N. Darwish
Mohamed N. Darwish has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11888047Abstract: Methods and systems for power semiconductor devices integrating multiple quasi-vertical transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.Type: GrantFiled: July 20, 2020Date of Patent: January 30, 2024Assignee: MaxPower Semiconductor, Inc.Inventors: Mohamed N. Darwish, Jun Zeng, Richard A. Blanchard
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Patent number: 11316021Abstract: A vertical transistor structure in which a recessed field plate trench surrounds multiple adjacent gate electrodes. Thus the specific on-state conductance is increased, since the ratio of recessed field plate area to channel area is reduced. Various versions use two, three, or more distinct gate electrodes within the interior of a single RFP or RSFP trench's layout.Type: GrantFiled: August 12, 2020Date of Patent: April 26, 2022Assignee: MaxPower Semiconductor Inc.Inventors: Mohamed N. Darwish, Jun Zeng, Richard A. Blanchard
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Patent number: 11289596Abstract: A split gate power device is disclosed having a trench containing a U-shaped gate that, when biased above a threshold voltage, creates a conductive channel in a p-well. Below the gate is a field plate in the trench, coupled to the source electrode, for spreading the electric field along the trench to improve the breakdown voltage. The top gate poly is initially formed relatively thin so that it can be patterned using non-CMP techniques, such as dry etching or wet etching. As such, the power device can be fabricated in conventional fabs not having CMP capability. In one embodiment, the thin gate has vertical and lateral portions that create conductive vertical and lateral channels in a p-well. In another embodiment, the thin gate has only vertical portions along the trench sidewalls for minimizing surface area and gate capacitance.Type: GrantFiled: February 5, 2020Date of Patent: March 29, 2022Assignee: MaxPower Semiconductor, Inc.Inventors: Jun Zeng, Kui Pu, Mohamed N. Darwish, Shih-Tzung Su
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Publication number: 20220052170Abstract: A vertical trench MOSFET is formed with deep P-shield regions below portions of each gate trench. The deep P-shield regions are effectively downward extensions of the P-body/well, and are electrically coupled to the top source electrode. The P-shield regions abut the bottom portions and lower sides of the gate trenches, so that those small portions of the gate trench do not create N-channels and do not conduct current. Accordingly, each trench comprises an active gate portion that creates an N-channel and a small non-active portion that abuts the P-shield regions. The spacing of the P-shield regions along each gate trench is selected to achieve the desired electric field spreading to protect the gate oxide from punch-through. No field plate trenches are needed to be formed in the active area of the MOSFET. The deep P-shield regions are formed by implanting P-type dopants through the bottom of the trenches.Type: ApplicationFiled: August 5, 2021Publication date: February 17, 2022Inventors: Jun Zeng, Mohamed N. Darwish, Shih-Tzung Su
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Publication number: 20210175348Abstract: Methods and systems for power semiconductor devices integrating multiple quasi-vertical transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.Type: ApplicationFiled: July 20, 2020Publication date: June 10, 2021Applicant: MaxPower Semiconductor Inc.Inventors: Mohamed N. Darwish, Jun Zeng, Richard A. Blanchard
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Publication number: 20210083061Abstract: A vertical transistor structure in which a recessed field plate trench surrounds multiple adjacent gate electrodes. Thus the specific on-state conductance is increased, since the ratio of recessed field plate area to channel area is reduced. Various versions use two, three, or more distinct gate electrodes within the interior of a single RFP or RSFP trench's layout.Type: ApplicationFiled: August 12, 2020Publication date: March 18, 2021Applicant: MaxPower Semiconductor Inc.Inventors: Mohamed N. Darwish, Jun Zeng, Richard A. Blanchard
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Publication number: 20200279926Abstract: Methods and systems for lateral power devices, and methods for operating them, in which charge balancing is implemented in a new way. In a first inventive teaching, the lateral conduction path is laterally flanked by regions of opposite conductivity type which are self-aligned to isolation trenches which define the surface geometry of the channel. In a second inventive teaching, which can be used separately or in synergistic combination with the first teaching, the drain regions are self-isolated. In a third inventive teaching, which can be used in synergistic combination with the first and/or second teachings, the source regions are also isolated from each other. In a fourth inventive teaching, the lateral conduction path is also overlain by an additional region of opposite conductivity type.Type: ApplicationFiled: December 5, 2019Publication date: September 3, 2020Applicant: MaxPower Semiconductor Inc.Inventors: Mohamed N. Darwish, Jun Zeng, Hamza Yilmaz, Richard A. Blanchard
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Publication number: 20200273987Abstract: A split gate power device is disclosed having a trench containing a U-shaped gate that, when biased above a threshold voltage, creates a conductive channel in a p-well. Below the gate is a field plate in the trench, coupled to the source electrode, for spreading the electric field along the trench to improve the breakdown voltage. The top gate poly is initially formed relatively thin so that it can be patterned using non-CMP techniques, such as dry etching or wet etching. As such, the power device can be fabricated in conventional fabs not having CMP capability. In one embodiment, the thin gate has vertical and lateral portions that create conductive vertical and lateral channels in a p-well. In another embodiment, the thin gate has only vertical portions along the trench sidewalls for minimizing surface area and gate capacitance.Type: ApplicationFiled: February 5, 2020Publication date: August 27, 2020Inventors: Jun Zeng, Kui Pu, Mohamed N. Darwish, Shih-Tzung Su
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Patent number: 10720511Abstract: Methods and systems for power semiconductor devices integrating multiple trench transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.Type: GrantFiled: October 1, 2018Date of Patent: July 21, 2020Assignee: MaxPower Semiconductor Inc.Inventors: Mohamed N. Darwish, Jun Zeng, Richard A. Blanchard
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Patent number: 10720510Abstract: Methods and systems for power semiconductor devices integrating multiple quasi-vertical transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.Type: GrantFiled: May 9, 2018Date of Patent: July 21, 2020Assignee: MaxPower Semiconductor Inc.Inventors: Mohamed N. Darwish, Jun Zeng, Richard A. Blanchard
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Publication number: 20200098856Abstract: Power devices using refilled trenches with permanent charge at or near their sidewalls. These trenches extend vertically into a drift region.Type: ApplicationFiled: June 12, 2019Publication date: March 26, 2020Applicant: MaxPower Semiconductor Inc.Inventors: Mohamed N. Darwish, Jun Zeng, Richard A. Blanchard
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Patent number: 10593813Abstract: A new semiconductor rectifier structure. In general, a MOS-transistor-like structure is located above a JFET-like deeper structure. The present application teaches ways to combine and optimize these two structures in a merged device so that the resulting combined structure achieves both a low forward voltage and a high reverse breakdown voltage in a relatively small area. In one class of innovative implementations, an insulated (or partially insulated) trench is used to define a vertical channel in a body region along the sidewall of a trench, so that majority carriers from a “source” region (typically n+) can flow through the channel. An added “pocket” diffusion, of the same conductivity type as the body region (p-type in this example), provides an intermediate region around the bottom of the trench. This intermediate diffusion, and an additional deep region of the same conductivity type, define a deep JFET-like device which is in series with the MOS channel portion of the diode.Type: GrantFiled: June 22, 2018Date of Patent: March 17, 2020Assignee: MaxPower Semiconductor Inc.Inventors: Richard A. Blanchard, Mohamed N. Darwish, Jun Zeng
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Patent number: 10529810Abstract: Methods and systems for lateral power devices, and methods for operating them, in which charge balancing is implemented in a new way. In a first inventive teaching, the lateral conduction path is laterally flanked by regions of opposite conductivity type which are self-aligned to isolation trenches which define the surface geometry of the channel. In a second inventive teaching, which can be used separately or in synergistic combination with the first teaching, the drain regions are self-isolated. In a third inventive teaching, which can be used in synergistic combination with the first and/or second teachings, the source regions are also isolated from each other. In a fourth inventive teaching, the lateral conduction path is also overlain by an additional region of opposite conductivity type.Type: GrantFiled: December 9, 2016Date of Patent: January 7, 2020Assignee: MaxPower Semiconductor, Inc.Inventors: Mohamed N. Darwish, Jun Zeng, Hamza Yilmaz, Richard A. Blanchard
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Publication number: 20200006499Abstract: Methods and systems for lateral power devices, and methods for operating them, in which charge balancing is implemented in a new way. In a first inventive teaching, the lateral conduction path is laterally flanked by regions of opposite conductivity type which are self-aligned to isolation trenches which define the surface geometry of the channel. In a second inventive teaching, which can be used separately or in synergistic combination with the first teaching, the drain regions are self-isolated. In a third inventive teaching, which can be used in synergistic combination with the first and/or second teachings, the source regions are also isolated from each other. In a fourth inventive teaching, the lateral conduction path is also overlain by an additional region of opposite conductivity type.Type: ApplicationFiled: December 9, 2016Publication date: January 2, 2020Applicant: MaxPower Semiconductor, Inc.Inventors: Mohamed N. Darwish, Jun Zeng, Hamza Yilmaz, Richard A. Blanchard
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Patent number: 10510863Abstract: In one embodiment, a power MOSFET vertically conducts current. A bottom electrode may be connected to a positive voltage, and a top electrode may be connected to a low voltage, such as a load connected to ground. A gate and/or a field plate, such as polysilicon, is within a trench. The trench has a tapered oxide layer insulating the polysilicon from the silicon walls. The oxide is much thicker near the bottom of the trench than near the top to increase the breakdown voltage. The tapered oxide is formed by implanting nitrogen into the trench walls to form a tapered nitrogen dopant concentration. This forms a tapered silicon nitride layer after an anneal. The tapered silicon nitride variably inhibits oxide growth in a subsequent oxidation step.Type: GrantFiled: August 14, 2017Date of Patent: December 17, 2019Assignee: MAXPOWER SEMICONDUCTOR, INC.Inventors: Richard A. Blanchard, Mohamed N. Darwish, Jun Zeng
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Patent number: 10325980Abstract: Power devices using refilled trenches with permanent charge at or near their sidewalls. These trenches extend vertically into a drift region.Type: GrantFiled: June 21, 2018Date of Patent: June 18, 2019Assignee: MaxPower Semiconductor Inc.Inventors: Mohamed N. Darwish, Jun Zeng, Richard A. Blanchard
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Publication number: 20190122926Abstract: Structures and fabrication methods for increasing the density of trench transistor devices and the like. During fabrication of a trench transistor device, a vertical protrusion (or “hat”) of oxide is left in place above the gate trench. This vertical protrusion is self-aligned to the gate trench, and is used to define the positions of sidewall spacers (made e.g. of silicon nitride). These sidewall spacers define a space outward from the edge of the gate trench; by performing a recess etch which is delimited by these sidewall spacers, the resistance of the source contact and the body contact is minimized. The spacing between the gate trench and the recessed-contact field-plate trench can therefore be minimized and well controlled, which improves density without degrading on-resistance nor breakdown voltage.Type: ApplicationFiled: August 28, 2018Publication date: April 25, 2019Applicant: MaxPower Semiconductor Inc.Inventors: Mohamed N. Darwish, Jun Zeng, Richard A. Blanchard
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Publication number: 20190123210Abstract: A lateral SOI device may include a semiconductor channel region connected to a drain region by a drift region. An insulation region on the drift layer is positioned between the channel region and the drain region. Permanent charges may be embedded in the insulation region sufficient to cause inversion in the insulation region. The semiconductor layer also overlies a global insulation layer, and permanent charges are preferably embedded in at least selected areas of this insulation layer too.Type: ApplicationFiled: July 23, 2018Publication date: April 25, 2019Applicant: MaxPower Semiconductor Inc.Inventors: Amit Paul, Mohamed N. Darwish
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Publication number: 20190115464Abstract: MOS-gated devices, related methods, and systems for vertical power and RF devices including an insulated trench and a gate electrode. A body region is positioned so that a voltage bias on the gate electrode will cause an inversion layer in the body region. Permanent electrostatic charges are included in said insulation material. A conductive shield layer is positioned above the insulated trench, to reduce parasitic capacitances.Type: ApplicationFiled: June 20, 2018Publication date: April 18, 2019Applicant: MaxPower Semiconductor Inc.Inventors: Mohamed N. Darwish, Jun Zeng
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Publication number: 20190097025Abstract: Methods and systems for power semiconductor devices integrating multiple trench transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.Type: ApplicationFiled: October 1, 2018Publication date: March 28, 2019Applicant: MaxPower Semiconductor Inc.Inventors: Mohamed N. Darwish, Jun Zeng, Richard A. Blanchard