Patents by Inventor Mohamed N. Darwish

Mohamed N. Darwish has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200279926
    Abstract: Methods and systems for lateral power devices, and methods for operating them, in which charge balancing is implemented in a new way. In a first inventive teaching, the lateral conduction path is laterally flanked by regions of opposite conductivity type which are self-aligned to isolation trenches which define the surface geometry of the channel. In a second inventive teaching, which can be used separately or in synergistic combination with the first teaching, the drain regions are self-isolated. In a third inventive teaching, which can be used in synergistic combination with the first and/or second teachings, the source regions are also isolated from each other. In a fourth inventive teaching, the lateral conduction path is also overlain by an additional region of opposite conductivity type.
    Type: Application
    Filed: December 5, 2019
    Publication date: September 3, 2020
    Applicant: MaxPower Semiconductor Inc.
    Inventors: Mohamed N. Darwish, Jun Zeng, Hamza Yilmaz, Richard A. Blanchard
  • Publication number: 20200273987
    Abstract: A split gate power device is disclosed having a trench containing a U-shaped gate that, when biased above a threshold voltage, creates a conductive channel in a p-well. Below the gate is a field plate in the trench, coupled to the source electrode, for spreading the electric field along the trench to improve the breakdown voltage. The top gate poly is initially formed relatively thin so that it can be patterned using non-CMP techniques, such as dry etching or wet etching. As such, the power device can be fabricated in conventional fabs not having CMP capability. In one embodiment, the thin gate has vertical and lateral portions that create conductive vertical and lateral channels in a p-well. In another embodiment, the thin gate has only vertical portions along the trench sidewalls for minimizing surface area and gate capacitance.
    Type: Application
    Filed: February 5, 2020
    Publication date: August 27, 2020
    Inventors: Jun Zeng, Kui Pu, Mohamed N. Darwish, Shih-Tzung Su
  • Patent number: 10720511
    Abstract: Methods and systems for power semiconductor devices integrating multiple trench transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: July 21, 2020
    Assignee: MaxPower Semiconductor Inc.
    Inventors: Mohamed N. Darwish, Jun Zeng, Richard A. Blanchard
  • Patent number: 10720510
    Abstract: Methods and systems for power semiconductor devices integrating multiple quasi-vertical transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: July 21, 2020
    Assignee: MaxPower Semiconductor Inc.
    Inventors: Mohamed N. Darwish, Jun Zeng, Richard A. Blanchard
  • Publication number: 20200098856
    Abstract: Power devices using refilled trenches with permanent charge at or near their sidewalls. These trenches extend vertically into a drift region.
    Type: Application
    Filed: June 12, 2019
    Publication date: March 26, 2020
    Applicant: MaxPower Semiconductor Inc.
    Inventors: Mohamed N. Darwish, Jun Zeng, Richard A. Blanchard
  • Patent number: 10593813
    Abstract: A new semiconductor rectifier structure. In general, a MOS-transistor-like structure is located above a JFET-like deeper structure. The present application teaches ways to combine and optimize these two structures in a merged device so that the resulting combined structure achieves both a low forward voltage and a high reverse breakdown voltage in a relatively small area. In one class of innovative implementations, an insulated (or partially insulated) trench is used to define a vertical channel in a body region along the sidewall of a trench, so that majority carriers from a “source” region (typically n+) can flow through the channel. An added “pocket” diffusion, of the same conductivity type as the body region (p-type in this example), provides an intermediate region around the bottom of the trench. This intermediate diffusion, and an additional deep region of the same conductivity type, define a deep JFET-like device which is in series with the MOS channel portion of the diode.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: March 17, 2020
    Assignee: MaxPower Semiconductor Inc.
    Inventors: Richard A. Blanchard, Mohamed N. Darwish, Jun Zeng
  • Patent number: 10529810
    Abstract: Methods and systems for lateral power devices, and methods for operating them, in which charge balancing is implemented in a new way. In a first inventive teaching, the lateral conduction path is laterally flanked by regions of opposite conductivity type which are self-aligned to isolation trenches which define the surface geometry of the channel. In a second inventive teaching, which can be used separately or in synergistic combination with the first teaching, the drain regions are self-isolated. In a third inventive teaching, which can be used in synergistic combination with the first and/or second teachings, the source regions are also isolated from each other. In a fourth inventive teaching, the lateral conduction path is also overlain by an additional region of opposite conductivity type.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: January 7, 2020
    Assignee: MaxPower Semiconductor, Inc.
    Inventors: Mohamed N. Darwish, Jun Zeng, Hamza Yilmaz, Richard A. Blanchard
  • Publication number: 20200006499
    Abstract: Methods and systems for lateral power devices, and methods for operating them, in which charge balancing is implemented in a new way. In a first inventive teaching, the lateral conduction path is laterally flanked by regions of opposite conductivity type which are self-aligned to isolation trenches which define the surface geometry of the channel. In a second inventive teaching, which can be used separately or in synergistic combination with the first teaching, the drain regions are self-isolated. In a third inventive teaching, which can be used in synergistic combination with the first and/or second teachings, the source regions are also isolated from each other. In a fourth inventive teaching, the lateral conduction path is also overlain by an additional region of opposite conductivity type.
    Type: Application
    Filed: December 9, 2016
    Publication date: January 2, 2020
    Applicant: MaxPower Semiconductor, Inc.
    Inventors: Mohamed N. Darwish, Jun Zeng, Hamza Yilmaz, Richard A. Blanchard
  • Patent number: 10510863
    Abstract: In one embodiment, a power MOSFET vertically conducts current. A bottom electrode may be connected to a positive voltage, and a top electrode may be connected to a low voltage, such as a load connected to ground. A gate and/or a field plate, such as polysilicon, is within a trench. The trench has a tapered oxide layer insulating the polysilicon from the silicon walls. The oxide is much thicker near the bottom of the trench than near the top to increase the breakdown voltage. The tapered oxide is formed by implanting nitrogen into the trench walls to form a tapered nitrogen dopant concentration. This forms a tapered silicon nitride layer after an anneal. The tapered silicon nitride variably inhibits oxide growth in a subsequent oxidation step.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: December 17, 2019
    Assignee: MAXPOWER SEMICONDUCTOR, INC.
    Inventors: Richard A. Blanchard, Mohamed N. Darwish, Jun Zeng
  • Patent number: 10325980
    Abstract: Power devices using refilled trenches with permanent charge at or near their sidewalls. These trenches extend vertically into a drift region.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: June 18, 2019
    Assignee: MaxPower Semiconductor Inc.
    Inventors: Mohamed N. Darwish, Jun Zeng, Richard A. Blanchard
  • Publication number: 20190123210
    Abstract: A lateral SOI device may include a semiconductor channel region connected to a drain region by a drift region. An insulation region on the drift layer is positioned between the channel region and the drain region. Permanent charges may be embedded in the insulation region sufficient to cause inversion in the insulation region. The semiconductor layer also overlies a global insulation layer, and permanent charges are preferably embedded in at least selected areas of this insulation layer too.
    Type: Application
    Filed: July 23, 2018
    Publication date: April 25, 2019
    Applicant: MaxPower Semiconductor Inc.
    Inventors: Amit Paul, Mohamed N. Darwish
  • Publication number: 20190122926
    Abstract: Structures and fabrication methods for increasing the density of trench transistor devices and the like. During fabrication of a trench transistor device, a vertical protrusion (or “hat”) of oxide is left in place above the gate trench. This vertical protrusion is self-aligned to the gate trench, and is used to define the positions of sidewall spacers (made e.g. of silicon nitride). These sidewall spacers define a space outward from the edge of the gate trench; by performing a recess etch which is delimited by these sidewall spacers, the resistance of the source contact and the body contact is minimized. The spacing between the gate trench and the recessed-contact field-plate trench can therefore be minimized and well controlled, which improves density without degrading on-resistance nor breakdown voltage.
    Type: Application
    Filed: August 28, 2018
    Publication date: April 25, 2019
    Applicant: MaxPower Semiconductor Inc.
    Inventors: Mohamed N. Darwish, Jun Zeng, Richard A. Blanchard
  • Publication number: 20190115464
    Abstract: MOS-gated devices, related methods, and systems for vertical power and RF devices including an insulated trench and a gate electrode. A body region is positioned so that a voltage bias on the gate electrode will cause an inversion layer in the body region. Permanent electrostatic charges are included in said insulation material. A conductive shield layer is positioned above the insulated trench, to reduce parasitic capacitances.
    Type: Application
    Filed: June 20, 2018
    Publication date: April 18, 2019
    Applicant: MaxPower Semiconductor Inc.
    Inventors: Mohamed N. Darwish, Jun Zeng
  • Publication number: 20190097025
    Abstract: Methods and systems for power semiconductor devices integrating multiple trench transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.
    Type: Application
    Filed: October 1, 2018
    Publication date: March 28, 2019
    Applicant: MaxPower Semiconductor Inc.
    Inventors: Mohamed N. Darwish, Jun Zeng, Richard A. Blanchard
  • Publication number: 20190067491
    Abstract: A new semiconductor rectifier structure. In general, a MOS-transistor-like structure is located above a JFET-like deeper structure. The present application teaches ways to combine and optimize these two structures in a merged device so that the resulting combined structure achieves both a low forward voltage and a high reverse breakdown voltage in a relatively small area. In one class of innovative implementations, an insulated (or partially insulated) trench is used to define a vertical channel in a body region along the sidewall of a trench, so that majority carriers from a “source” region (typically n+) can flow through the channel. An added “pocket” diffusion, of the same conductivity type as the body region (p-type in this example), provides an intermediate region around the bottom of the trench. This intermediate diffusion, and an additional deep region of the same conductivity type, define a deep JFET-like device which is in series with the MOS channel portion of the diode.
    Type: Application
    Filed: June 22, 2018
    Publication date: February 28, 2019
    Applicant: MaxPower Semiconductor Inc.
    Inventors: Richard A. Blanchard, Mohamed N. Darwish, Jun Zeng
  • Publication number: 20190051743
    Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type formed thereon. The semiconductor device also includes a body layer extending a first predetermined distance into the semiconductor layer of the second conductivity type and a pair of trenches extending a second predetermined distance into the semiconductor layer of the second conductivity type. Each of the pair of trenches consists essentially of a dielectric material disposed therein and a concentration of doping impurities present in the semiconductor layer of the second conductivity type and a distance between the pair of trenches define an electrical characteristic of the semiconductor device. The semiconductor device further includes a control gate coupled to the semiconductor layer of the second conductivity type and a source region coupled to the semiconductor layer of the second conductivity type.
    Type: Application
    Filed: January 24, 2017
    Publication date: February 14, 2019
    Applicant: MaxPower Semiconductor, Inc.
    Inventor: Mohamed N. Darwish
  • Patent number: 10186573
    Abstract: In one embodiment, a RESURF structure between a source and a drain in a lateral MOSFET is formed in a trench having a flat bottom surface and angled sidewalls toward the source. Alternating P and N-type layers are epitaxially grown in the trench, and their charges balanced to achieve a high breakdown voltage. In the area of the source, the ends of the P and N-layers angle upward to the surface under the lateral gate and contact the body region. Thus, for an N-channel MOSFET, a positive gate voltage above the threshold forms a channel between the source and the N-layers in the RESURF structure as well as creates an inversion of the ends of the P-layers near the surface for low on-resistance. In another embodiment, the RESURF structure is vertically corrugated by being formed around trenches, thus extending the length of the RESURF structure for a higher breakdown voltage.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: January 22, 2019
    Assignee: MaxPower Semiconductor, Inc.
    Inventors: Hamza Yilmaz, Mohamed N. Darwish, Richard A. Blanchard
  • Publication number: 20180366569
    Abstract: Heterostructure and double-heterostructure trench-gate devices, in which the substrate and/or the body are constructed of a narrower-bandgap semiconductor material than the uppermost portion of the drift region. Fabrication most preferably uses a process where gate dielectric anneal is performed after all other high-temperature steps have already been done.
    Type: Application
    Filed: June 12, 2018
    Publication date: December 20, 2018
    Applicant: MaxPower Semiconductor Inc.
    Inventors: Jun Zeng, Mohamed N. Darwish
  • Patent number: 10157983
    Abstract: In one embodiment, a power MOSFET or IGBT cell includes an N-type drift region grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed over the drift region. A P-well is formed over the N-type layer, and an N+ source/emitter region is formed in the P-well. A gate is formed over the P-well's lateral channel and has a vertical extension into a trench. A positive gate voltage inverts the lateral channel and increases the vertical conduction in the N-type layer along the sidewalls of the trench to reduce on-resistance. A vertical shield field plate is also in the trench and may be connected to the gate. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage. Floating P-islands in the N-type drift region increase breakdown voltage and reduce the saturation current.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: December 18, 2018
    Assignee: MAXPOWER SEMICONDUCTOR INC.
    Inventors: Jun Zeng, Mohamed N. Darwish, Wenfang Du, Richard A. Blanchard, Kui Pu, Shih-Tzung Su
  • Publication number: 20180358449
    Abstract: A silicon carbide (or comparable) trench transistor in which gate dielectric anneal, in an oxynitriding atmosphere, is performed after all other high-temperature steps have already been done.
    Type: Application
    Filed: June 12, 2017
    Publication date: December 13, 2018
    Applicant: MaxPower Semiconductor Inc.
    Inventors: Jun Zeng, Mohamed N. Darwish