Patents by Inventor Mohammed A. Hassan

Mohammed A. Hassan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040052846
    Abstract: Delivery of a drug is controlled to impart a delay before release after administration by formulating the drug with a disruption agent to provide a core, and coating the core with a regulatory membrane comprising a water-soluble gel-forming polymer and a water-insoluble film-forming polymer.
    Type: Application
    Filed: September 30, 2003
    Publication date: March 18, 2004
    Inventors: Derek Allan Prater, Mohammed Hassan, Christopher Robert Bland
  • Patent number: 6587378
    Abstract: In a Flash memory unit, the storage of a logic signal in the memory cells is determined by performing a READ operation. The NORMAL READ operation requires that the floating gate store an amount of charge QNR above which a logic “0” is identified and below which a logic “1” is identified as being stored in the memory cell. A second level of charge QTR stored on the floating gate is used in a TEST READ operation. The stored charge QTR is greater than the stored charge QNR, but less than the charge stored on the floating gate as the result of a WRITE operation. The result of a TEST READ operation is compared with a NORMAL READ operation of a memory cell. When the logic state identified by the TEST READ operation and the NORMAL READ operation are not the same, the charge on the cell is determined to have decayed below a prescribed level and the memory cell is refreshed to the level that is present during a WRITE operation.
    Type: Grant
    Filed: December 13, 2001
    Date of Patent: July 1, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Mohammed A. Hassan, Robert M. Crosby, Clyde F. Dunn, Andrew M. Love
  • Publication number: 20020110028
    Abstract: In a Flash memory unit, the storage of a logic signal in the memory cells is determined by performing a READ operation. The NORMAL READ operation requires that the floating gate store an amount of charge QNR above which a logic “0” is identified and below which a logic “1” is identified as being stored in the memory cell. A second level of charge QTR stored on the floating gate is used in a TEST READ operation. The stored charge QTR is greater than the stored charge QNR, but less than the charge stored on the floating gate as the result of a WRITE operation. The result of a TEST READ operation is compared with a NORMAL READ operation of a memory cell. When the logic state identified by the TEST READ operation and the NORMAL READ operation are not the same, the charge on the cell is determined to have decayed below a prescribed level and the memory cell is refreshed to the level that is present during a WRITE operation.
    Type: Application
    Filed: December 13, 2001
    Publication date: August 15, 2002
    Inventors: Mohammed A. Hassan, Robert M. Crosby, Clyde F. Dunn, Andrew M. Love
  • Patent number: D440953
    Type: Grant
    Filed: October 2, 2000
    Date of Patent: April 24, 2001
    Assignee: Hughes Electronics Corporation
    Inventors: Mohammed Hassan Omran, Alex Toh, Aaron Palumbo, Graham Avis, Charles Curbbun, Chris Borowiecki