Patents by Inventor Mohammed Rabiul Islam

Mohammed Rabiul Islam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11966090
    Abstract: Heterogeneous packaging integration of photonic and electronic elements is described herein. In one embodiment, a disclosed package includes: a package substrate; a first layer comprising an electronic die on the package substrate; and a second layer comprising a photonic die. The second layer is bonded onto the first layer such that the photonic die is bonded onto the electronic die.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Stefan Rusu, Wei-Wei Song, Mohammed Rabiul Islam
  • Publication number: 20240012975
    Abstract: A method of forming an integrated circuit structure is provided. The method includes: providing a logic cell structure including a first input node, a second input node, and a pulling network connected to a reference voltage and an output node, wherein the pulling network includes a plurality of transistor segments; determining a delay associated with at least one of the first input node and the second input node; and connecting the plurality of transistor segments to the first input node, the second input node and the output node based at least in part on the determined delay.
    Type: Application
    Filed: September 22, 2023
    Publication date: January 11, 2024
    Inventors: KUMAR LALGUDI, RANJITH KUMAR, MOHAMMED RABIUL ISLAM, JIANYANG XU
  • Publication number: 20230393337
    Abstract: Structures and methods for high speed interconnection in photonic systems are described herein. In one embodiment, a photonic device is disclosed. The photonic device includes: a substrate; a plurality of metal layers on the substrate; a photonic material layer comprising graphene over the plurality of metal layers; and an optical routing layer comprising a waveguide on the photonic material layer.
    Type: Application
    Filed: August 9, 2023
    Publication date: December 7, 2023
    Inventors: Weiwei SONG, Stefan RUSU, Mohammed Rabiul ISLAM
  • Patent number: 11816412
    Abstract: A method of forming an integrated circuit structure is provided. The method includes: providing a logic cell structure including a first input node, a second input node, and a pulling network connected to a reference voltage and an output node, wherein the pulling network includes a plurality of transistor segments; determining a delay associated with at least one of the first input node and the second input node; and connecting the plurality of transistor segments to the first input node, the second input node and the output node based at least in part on the determined delay.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: November 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Kumar Lalgudi, Ranjith Kumar, Mohammed Rabiul Islam, Jianyang Xu
  • Patent number: 11808977
    Abstract: Structures and methods for high speed interconnection in photonic systems are described herein. In one embodiment, a photonic device is disclosed. The photonic device includes: a substrate; a plurality of metal layers on the substrate; a photonic material layer comprising graphene over the plurality of metal layers; and an optical routing layer comprising a waveguide on the photonic material layer.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: November 7, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Weiwei Song, Stefan Rusu, Mohammed Rabiul Islam
  • Publication number: 20230305226
    Abstract: A structure includes an optical interposer attached to a package substrate, wherein the optical interposer includes a silicon waveguide, a first photonic component optically coupled to the silicon waveguide, a second photonic component optically coupled to the silicon waveguide, and an interconnect structure extending over the silicon waveguide, over the first photonic component, and over the second photonic component, wherein the interconnect structure is electrically connected to the first photonic component and to the second photonic component, a first semiconductor device attached to the interconnect structure, wherein the first semiconductor device is electrically connected to the first photonic component through the interconnect structure, and a second semiconductor device attached to the interconnect structure, wherein the second semiconductor device is electrically connected to the second photonic component through the interconnect structure.
    Type: Application
    Filed: June 1, 2023
    Publication date: September 28, 2023
    Inventors: Mohammed Rabiul Islam, Stefan Rusu, Weiwei Song
  • Publication number: 20230237237
    Abstract: An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.
    Type: Application
    Filed: March 27, 2023
    Publication date: July 27, 2023
    Inventors: Po-Chia Lai, Kuo-Ji Chen, Wen-Hao Chen, Wun-Jie Lin, Yu-Ti Su, Mohammed Rabiul Islam, Shu-Yi Ying, Stefan Rusu, Kuan-Te Li, David Barry Scott
  • Patent number: 11703639
    Abstract: A structure includes an optical interposer attached to a package substrate, wherein the optical interposer includes a silicon waveguide, a first photonic component optically coupled to the silicon waveguide, a second photonic component optically coupled to the silicon waveguide, and an interconnect structure extending over the silicon waveguide, over the first photonic component, and over the second photonic component, wherein the interconnect structure is electrically connected to the first photonic component and to the second photonic component, a first semiconductor device attached to the interconnect structure, wherein the first semiconductor device is electrically connected to the first photonic component through the interconnect structure, and a second semiconductor device attached to the interconnect structure, wherein the second semiconductor device is electrically connected to the second photonic component through the interconnect structure.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: July 18, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mohammed Rabiul Islam, Stefan Rusu, Weiwei Song
  • Publication number: 20230114059
    Abstract: Structures and methods for high speed interconnection in photonic systems are described herein. In one embodiment, a photonic device is disclosed. The photonic device includes: a substrate; a plurality of metal layers on the substrate; a photonic material layer comprising graphene over the plurality of metal layers; and an optical routing layer comprising a waveguide on the photonic material layer.
    Type: Application
    Filed: December 13, 2022
    Publication date: April 13, 2023
    Inventors: Weiwei SONG, Stefan RUSU, Mohammed Rabiul ISLAM
  • Patent number: 11550102
    Abstract: Structures and methods for high speed interconnection in photonic systems are described herein. In one embodiment, a photonic device is disclosed. The photonic device includes: a substrate; a plurality of metal layers on the substrate; a photonic material layer comprising graphene over the plurality of metal layers; and an optical routing layer comprising a waveguide on the photonic material layer.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: January 10, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Weiwei Song, Stefan Rusu, Mohammed Rabiul Islam
  • Publication number: 20220382005
    Abstract: Disclosed are apparatus and methods for optical interconnections that include the integration of a photonics die @Die) and an electronic die (eDie) with a socket layer, waveguides and fiber connectors to enable high bandwidth communications. In one embodiment, an exemplary optical interconnect device includes an electronic die coupled to a photonics die and integrated with a substrate, a socket, a board, a pair of micro-lenses and a mirror coupled to a waveguide, which can be embedded in the board. In another embodiment, the waveguide is embedded in a socket layer and coupled to a fiber connector. In these embodiments, the exemplary optical interface device can be coupled one more other optical interconnect devices via a waveguide array and/or a fiber array.
    Type: Application
    Filed: May 28, 2021
    Publication date: December 1, 2022
    Inventors: Stefan RUSU, Wei-wei SONG, Mohammed Rabiul ISLAM, Chih-Tsung SHIH
  • Publication number: 20220335191
    Abstract: A method of forming an integrated circuit structure is provided. The method includes: providing a logic cell structure including a first input node, a second input node, and a pulling network connected to a reference voltage and an output node, wherein the pulling network includes a plurality of transistor segments; determining a delay associated with at least one of the first input node and the second input node; and connecting the plurality of transistor segments to the first input node, the second input node and the output node based at least in part on the determined delay.
    Type: Application
    Filed: April 16, 2021
    Publication date: October 20, 2022
    Inventors: KUMAR LALGUDI, RANJITH KUMAR, MOHAMMED RABIUL ISLAM, JIANYANG XU
  • Publication number: 20220302089
    Abstract: A three-dimensional integrated circuit (3D IC) package is provided. The 3D IC package includes: a cache die including a low-dropout (LDO) regulator and a cache memory device; a compute die above the cache die, the compute die including a processor; and one or more first interconnect structures connecting the cache die and the compute die in a vertical direction.
    Type: Application
    Filed: December 22, 2021
    Publication date: September 22, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Stefan Rusu, Mohammed Rabiul Islam, Eric Soenen
  • Publication number: 20220283387
    Abstract: Heterogeneous packaging integration of photonic and electronic elements is described herein. In one embodiment, a disclosed package includes: a package substrate; a first layer comprising an electronic die on the package substrate; and a second layer comprising a photonic die. The second layer is bonded onto the first layer such that the photonic die is bonded onto the electronic die.
    Type: Application
    Filed: March 3, 2021
    Publication date: September 8, 2022
    Inventors: Stefan RUSU, Wei-wei Song, Mohammed Rabiul Islam
  • Publication number: 20220128759
    Abstract: A structure includes an optical interposer attached to a package substrate, wherein the optical interposer includes a silicon waveguide, a first photonic component optically coupled to the silicon waveguide, a second photonic component optically coupled to the silicon waveguide, and an interconnect structure extending over the silicon waveguide, over the first photonic component, and over the second photonic component, wherein the interconnect structure is electrically connected to the first photonic component and to the second photonic component, a first semiconductor device attached to the interconnect structure, wherein the first semiconductor device is electrically connected to the first photonic component through the interconnect structure, and a second semiconductor device attached to the interconnect structure, wherein the second semiconductor device is electrically connected to the second photonic component through the interconnect structure.
    Type: Application
    Filed: January 3, 2022
    Publication date: April 28, 2022
    Inventors: Mohammed Rabiul Islam, Stefan Rusu, Weiwei Song
  • Publication number: 20220066099
    Abstract: Structures and methods for high speed interconnection in photonic systems are described herein. In one embodiment, a photonic device is disclosed. The photonic device includes: a substrate; a plurality of metal layers on the substrate; a photonic material layer comprising graphene over the plurality of metal layers; and an optical routing layer comprising a waveguide on the photonic material layer.
    Type: Application
    Filed: August 31, 2020
    Publication date: March 3, 2022
    Inventors: Weiwei SONG, Stefan RUSU, Mohammed Rabiul ISLAM
  • Patent number: 11215753
    Abstract: A structure includes an optical interposer attached to a package substrate, wherein the optical interposer includes a silicon waveguide, a first photonic component optically coupled to the silicon waveguide, a second photonic component optically coupled to the silicon waveguide, and an interconnect structure extending over the silicon waveguide, over the first photonic component, and over the second photonic component, wherein the interconnect structure is electrically connected to the first photonic component and to the second photonic component, a first semiconductor device attached to the interconnect structure, wherein the first semiconductor device is electrically connected to the first photonic component through the interconnect structure, and a second semiconductor device attached to the interconnect structure, wherein the second semiconductor device is electrically connected to the second photonic component through the interconnect structure.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: January 4, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mohammed Rabiul Islam, Stefan Rusu, Weiwei Song
  • Publication number: 20210271020
    Abstract: A structure includes an optical interposer attached to a package substrate, wherein the optical interposer includes a silicon waveguide, a first photonic component optically coupled to the silicon waveguide, a second photonic component optically coupled to the silicon waveguide, and an interconnect structure extending over the silicon waveguide, over the first photonic component, and over the second photonic component, wherein the interconnect structure is electrically connected to the first photonic component and to the second photonic component, a first semiconductor device attached to the interconnect structure, wherein the first semiconductor device is electrically connected to the first photonic component through the interconnect structure, and a second semiconductor device attached to the interconnect structure, wherein the second semiconductor device is electrically connected to the second photonic component through the interconnect structure.
    Type: Application
    Filed: February 27, 2020
    Publication date: September 2, 2021
    Inventors: Mohammed Rabiul Islam, Stefan Rusu, Weiwei Song
  • Publication number: 20210117605
    Abstract: An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.
    Type: Application
    Filed: December 21, 2020
    Publication date: April 22, 2021
    Inventors: Po-Chia Lai, Kuo-Ji Chen, Wen-Hao Chen, Wun-Jie Lin, Yu-Ti Su, Mohammed Rabiul Islam, Shu-Yi Ying, Stefan Rusu, Kuan-Te Li, David Barry Scott
  • Patent number: 6573173
    Abstract: A copper interconnect polishing process begins by polishing (17) a bulk thickness of copper (63) using a first platen. A second platen is then used to remove (19) a thin remaining interfacial copper layer to expose a barrier film (61). Computer control (21) monitors polish times of the first and second platen and adjusts these times to improve wafer throughput. One or more platens and/or the wafer is rinsed (20) between the interfacial copper polish and the barrier polish to reduce slurry cross contamination. A third platen and slurry is then used to polish away exposed portions of the barrier (61) to complete polishing of the copper interconnect structure. A holding tank that contains anti-corrosive fluid is used to queue the wafers until subsequent scrubbing operations (25). A scrubbing operation (25) that is substantially void of light is used to reduce photovoltaic induced corrosion of copper in the drying chamber of the scubber.
    Type: Grant
    Filed: June 20, 2002
    Date of Patent: June 3, 2003
    Assignee: Motorola, Inc.
    Inventors: Janos Farkas, Brian G. Anthony, Abbas Guvenilir, Mohammed Rabiul Islam, Venkat Kolagunta, John Mendonca, Rajesh Tiwari, Suresh Venkatesan