Abstract: A structure includes an optical interposer attached to a package substrate, wherein the optical interposer includes a silicon waveguide, a first photonic component optically coupled to the silicon waveguide, a second photonic component optically coupled to the silicon waveguide, and an interconnect structure extending over the silicon waveguide, over the first photonic component, and over the second photonic component, wherein the interconnect structure is electrically connected to the first photonic component and to the second photonic component, a first semiconductor device attached to the interconnect structure, wherein the first semiconductor device is electrically connected to the first photonic component through the interconnect structure, and a second semiconductor device attached to the interconnect structure, wherein the second semiconductor device is electrically connected to the second photonic component through the interconnect structure.

Abstract: A three-dimensional integrated circuit (3D IC) package is provided. The 3D IC package includes: a cache die including a low-dropout (LDO) regulator and a cache memory device; a compute die above the cache die, the compute die including a processor; and one or more first interconnect structures connecting the cache die and the compute die in a vertical direction.

Abstract: A structure includes an optical interposer attached to a package substrate, wherein the optical interposer includes a silicon waveguide, a first photonic component optically coupled to the silicon waveguide, a second photonic component optically coupled to the silicon waveguide, and an interconnect structure extending over the silicon waveguide, over the first photonic component, and over the second photonic component, wherein the interconnect structure is electrically connected to the first photonic component and to the second photonic component, a first semiconductor device attached to the interconnect structure, wherein the first semiconductor device is electrically connected to the first photonic component through the interconnect structure, and a second semiconductor device attached to the interconnect structure, wherein the second semiconductor device is electrically connected to the second photonic component through the interconnect structure.

Abstract: A three-dimensional integrated circuit (3D IC) package is provided. The 3D IC package includes: a cache die including a low-dropout (LDO) regulator and a cache memory device; a compute die above the cache die, the compute die including a processor; and one or more first interconnect structures connecting the cache die and the compute die in a vertical direction.

Abstract: Heterogeneous packaging integration of photonic and electronic elements is described herein. In one embodiment, a disclosed package includes: a package substrate; a first layer comprising an electronic die on the package substrate; and a second layer comprising a photonic die. The second layer is bonded onto the first layer such that the photonic die is bonded onto the electronic die.

Abstract: Heterogeneous packaging integration of photonic and electronic elements is described herein. In one embodiment, a disclosed package includes: a package substrate; a first layer comprising an electronic die on the package substrate; and a second layer comprising a photonic die. The second layer is bonded onto the first layer such that the photonic die is bonded onto the electronic die.

Abstract: A method of forming an integrated circuit structure is provided. The method includes: providing a logic cell structure including a first input node, a second input node, and a pulling network connected to a reference voltage and an output node, wherein the pulling network includes a plurality of transistor segments; determining a delay associated with at least one of the first input node and the second input node; and connecting the plurality of transistor segments to the first input node, the second input node and the output node based at least in part on the determined delay.

Abstract: Structures and methods for high speed interconnection in photonic systems are described herein. In one embodiment, a photonic device is disclosed. The photonic device includes: a substrate; a plurality of metal layers on the substrate; a photonic material layer comprising graphene over the plurality of metal layers; and an optical routing layer comprising a waveguide on the photonic material layer.

Abstract: A method of forming an integrated circuit structure is provided. The method includes: providing a logic cell structure including a first input node, a second input node, and a pulling network connected to a reference voltage and an output node, wherein the pulling network includes a plurality of transistor segments; determining a delay associated with at least one of the first input node and the second input node; and connecting the plurality of transistor segments to the first input node, the second input node and the output node based at least in part on the determined delay.

Abstract: Structures and methods for high speed interconnection in photonic systems are described herein. In one embodiment, a photonic device is disclosed. The photonic device includes: a substrate; a plurality of metal layers on the substrate; a photonic material layer comprising graphene over the plurality of metal layers; and an optical routing layer comprising a waveguide on the photonic material layer.

Abstract: A structure includes an optical interposer attached to a package substrate, wherein the optical interposer includes a silicon waveguide, a first photonic component optically coupled to the silicon waveguide, a second photonic component optically coupled to the silicon waveguide, and an interconnect structure extending over the silicon waveguide, over the first photonic component, and over the second photonic component, wherein the interconnect structure is electrically connected to the first photonic component and to the second photonic component, a first semiconductor device attached to the interconnect structure, wherein the first semiconductor device is electrically connected to the first photonic component through the interconnect structure, and a second semiconductor device attached to the interconnect structure, wherein the second semiconductor device is electrically connected to the second photonic component through the interconnect structure.

Abstract: An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.

Abstract: A structure includes an optical interposer attached to a package substrate, wherein the optical interposer includes a silicon waveguide, a first photonic component optically coupled to the silicon waveguide, a second photonic component optically coupled to the silicon waveguide, and an interconnect structure extending over the silicon waveguide, over the first photonic component, and over the second photonic component, wherein the interconnect structure is electrically connected to the first photonic component and to the second photonic component, a first semiconductor device attached to the interconnect structure, wherein the first semiconductor device is electrically connected to the first photonic component through the interconnect structure, and a second semiconductor device attached to the interconnect structure, wherein the second semiconductor device is electrically connected to the second photonic component through the interconnect structure.

Abstract: Structures and methods for high speed interconnection in photonic systems are described herein. In one embodiment, a photonic device is disclosed. The photonic device includes: a substrate; a plurality of metal layers on the substrate; a photonic material layer comprising graphene over the plurality of metal layers; and an optical routing layer comprising a waveguide on the photonic material layer.

Abstract: Structures and methods for high speed interconnection in photonic systems are described herein. In one embodiment, a photonic device is disclosed. The photonic device includes: a substrate; a plurality of metal layers on the substrate; a photonic material layer comprising graphene over the plurality of metal layers; and an optical routing layer comprising a waveguide on the photonic material layer.

Abstract: Disclosed are apparatus and methods for optical interconnections that include the integration of a photonics die @Die) and an electronic die (eDie) with a socket layer, waveguides and fiber connectors to enable high bandwidth communications. In one embodiment, an exemplary optical interconnect device includes an electronic die coupled to a photonics die and integrated with a substrate, a socket, a board, a pair of micro-lenses and a mirror coupled to a waveguide, which can be embedded in the board. In another embodiment, the waveguide is embedded in a socket layer and coupled to a fiber connector. In these embodiments, the exemplary optical interface device can be coupled one more other optical interconnect devices via a waveguide array and/or a fiber array.

Abstract: A method of forming an integrated circuit structure is provided. The method includes: providing a logic cell structure including a first input node, a second input node, and a pulling network connected to a reference voltage and an output node, wherein the pulling network includes a plurality of transistor segments; determining a delay associated with at least one of the first input node and the second input node; and connecting the plurality of transistor segments to the first input node, the second input node and the output node based at least in part on the determined delay.

Abstract: A three-dimensional integrated circuit (3D IC) package is provided. The 3D IC package includes: a cache die including a low-dropout (LDO) regulator and a cache memory device; a compute die above the cache die, the compute die including a processor; and one or more first interconnect structures connecting the cache die and the compute die in a vertical direction.

Abstract: Heterogeneous packaging integration of photonic and electronic elements is described herein. In one embodiment, a disclosed package includes: a package substrate; a first layer comprising an electronic die on the package substrate; and a second layer comprising a photonic die. The second layer is bonded onto the first layer such that the photonic die is bonded onto the electronic die.

Abstract: A structure includes an optical interposer attached to a package substrate, wherein the optical interposer includes a silicon waveguide, a first photonic component optically coupled to the silicon waveguide, a second photonic component optically coupled to the silicon waveguide, and an interconnect structure extending over the silicon waveguide, over the first photonic component, and over the second photonic component, wherein the interconnect structure is electrically connected to the first photonic component and to the second photonic component, a first semiconductor device attached to the interconnect structure, wherein the first semiconductor device is electrically connected to the first photonic component through the interconnect structure, and a second semiconductor device attached to the interconnect structure, wherein the second semiconductor device is electrically connected to the second photonic component through the interconnect structure.