Patents by Inventor Mohan J. Kumar

Mohan J. Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160378623
    Abstract: Embodiments are generally directed to high capacity energy backed memory with off device storage. A memory device includes a circuit board; multiple memory chips that are installed on the circuit board; a controller to provide for backing up contents of the memory chips when a power loss condition is detected; a connection to a backup energy source; and a connection to a backup data storage that is separate from the memory device.
    Type: Application
    Filed: June 26, 2015
    Publication date: December 29, 2016
    Inventors: Mohan J. Kumar, Murugasamy K. Nachimuthu, George Vergis
  • Publication number: 20160349817
    Abstract: Power protecting a memory subsystem with a centralized storage device. A centralized backup energy source provides power temporarily when power supply power is interrupted. In response to detecting interruption of power supply power, a controller selectively connects multiple selected memory devices to a centralized SATA (serial advanced technology attachment) storage device to transfer contents of the selected memory devices to the storage device while powered by the backup energy source.
    Type: Application
    Filed: December 26, 2015
    Publication date: December 1, 2016
    Inventors: Mohan J. Kumar, Murugasamy K. Nachimuthu, George Vergis
  • Publication number: 20160350002
    Abstract: A system enables memory device specific self-refresh entry and exit commands. When memory devices on a shared control bus (such as all memory devices in a rank) are in self-refresh, a memory controller can issue a device specific command with a self-refresh exit command and a unique memory device identifier to the memory device. The controller sends the command over the shared control bus, and only the selected, identified memory device will exit self-refresh while the other devices will ignore the command and remain in self-refresh. The controller can then execute data access over a shared data bus with the specific memory device while the other memory devices are in self-refresh.
    Type: Application
    Filed: December 26, 2015
    Publication date: December 1, 2016
    Inventors: George Vergis, Kuljit S. Bains, James A. McCall, Murugasamy K. Nachimuthu, Mohan J. Kumar
  • Publication number: 20160343453
    Abstract: Disclosed is an apparatus and a method to inject errors to a memory. In one embodiment, a dedicated interface includes an error injection system address register and an error injection mask register coupled to the error injection system address register. If the error injection system address register includes a system address that matches an incoming write address, the error injection mask register outputs an error to the memory.
    Type: Application
    Filed: August 2, 2016
    Publication date: November 24, 2016
    Inventors: Theodros Yigzaw, Kai Cheng, Mohan J. Kumar, Jose A. Vargas, Gopikrishna Jandhyala
  • Publication number: 20160308723
    Abstract: The present disclosure is directed to capability determination for computing resource allocation. A device may comprise a management engine (ME) to determine device information for use in generating an enhanced universally unique identifier (UUID) based on a UUID corresponding to the device. The ME may interact with equipment in the device to obtain the device information, and may augment the UUID using at least part of the device information. Device information may include a device media access control (MAC) address, a central processing unit (CPU) identification (ID) for at least one CPU in the device and a device capability ID. The capability ID may be generated utilizing capability information obtained from the equipment, and may be encoded into the capability ID based on tables that describe different capabilities. The device may provide the enhanced UUID to a group agent that may group the device with other devices comprising similar capabilities.
    Type: Application
    Filed: December 31, 2013
    Publication date: October 20, 2016
    Applicant: INTEL CORPORATION
    Inventors: MRITTIKA GANGULI, JAIBER J. JOHN, MOHAN J. KUMAR, TESSIL THOMAS
  • Patent number: 9465647
    Abstract: In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: October 11, 2016
    Assignee: Intel Corporation
    Inventors: Mahesh Natu, Thanunathan Rangarajan, Gautam Doshi, Shamanna M. Datta, Baskaran Ganesan, Mohan J. Kumar, Rajesh S. Parthasarathy, Frank Binns, Rajesh Nagaraja Murthy, Robert C. Swanson
  • Patent number: 9448867
    Abstract: A method is described that includes detecting that a memory access of system management mode program code is attempting to reach program code outside of a protected region of memory by comparing a target memory address of a memory access instruction of the system management program code again information that defines confines of the protection region. The method also includes raising an error signal in response to the detecting.
    Type: Grant
    Filed: December 31, 2011
    Date of Patent: September 20, 2016
    Assignee: Intel Corporation
    Inventors: Shamanna M. Datta, Rajesh S. Parathasarathy, Mahesh S. Natu, Frank Binns, Mohan J. Kumar
  • Patent number: 9448879
    Abstract: An apparatus and method are described for detecting and correcting instruction fetch errors within a processor core. For example, in one embodiment, an instruction processing apparatus for detecting and recovering from instruction fetch errors comprises, the instruction processing apparatus performing the operations of: detecting an error associated with an instruction in response to an instruction fetch operation; and determining if the instruction is from a speculative access, wherein if the instruction is not from a speculative access, then responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: September 20, 2016
    Assignee: INTEL CORPORATION
    Inventors: Theodros Yigzaw, Oded Lempel, Hisham Shafi, Geeyarpuram N. Santhanakrishnan, Jose A. Vargas, Ganapati N Srinivasa, Mohan J Kumar, Larisa Novakovsky, Lihu Rappoport, Chen Koren, Julius Mandelblat, Michael Mishaeli
  • Publication number: 20160239460
    Abstract: Systems and methods of implementing server architectures that can facilitate the servicing of memory components in computer systems. The systems and methods employ nonvolatile memory/storage modules that include nonvolatile memory (NVM) that can be used for system memory and mass storage, as well as firmware memory. The respective NVM/storage modules can be received in front or rear-loading bays of the computer systems. The systems and methods further employ single, dual, or quad socket processors, in which each processor is communicably coupled to at least some of the NVM/storage modules disposed in the front or rear-loading bays by one or more memory and/or input/output (I/O) channels. By employing NVM/storage modules that can be received in front or rear-loading bays of computer systems, the systems and methods provide memory component serviceability heretofore unachievable in computer systems implementing conventional server architectures.
    Type: Application
    Filed: November 27, 2013
    Publication date: August 18, 2016
    Inventors: Dimitrios Ziakas, Bassam N. Coury, Mohan J. Kumar, Murugasamy K. Nachimuthu, Thi Dang, Russell J. Wunderlich
  • Patent number: 9411667
    Abstract: Embodiments of apparatus, computer-implemented methods, systems, devices, and computer-readable media are described herein for a computing device with a platform entity such as an interrupt handier configured to notify an operating system or virtual machine monitor executing on the computing device of an input/output error-containment event. In various embodiments, the interrupt handler may be configured to facilitate recovery of a link to an input/output device that caused the input/output error-containment event, responsive to a directive from the operating system or virtual machine monitor.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: August 9, 2016
    Assignee: Intel Corporation
    Inventors: Sarathy Jayakumar, Mohan J. Kumar, Jose A. Vargas
  • Patent number: 9405646
    Abstract: Disclosed is an apparatus and a method to inject errors to a memory. In one embodiment, a dedicated interface includes an error injection system address register and an error injection mask register coupled to the error injection system address register. If the error injection system address register includes a system address that matches an incoming write address, the error injection mask register outputs an error to the memory.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: August 2, 2016
    Inventors: Theodros Yigzaw, Kai Cheng, Mohan J. Kumar, Jose A. Vargas, Gopikrishna Jandhyala
  • Patent number: 9383932
    Abstract: An apparatus for providing data coherency is described herein. The apparatus includes a global persistent memory. The global persistent memory is accessed using a protocol that includes input/output (I/O) semantics and memory semantics. The apparatus also includes a reflected memory region. The reflected memory region is a portion of the global persistent memory, and each node of a plurality of nodes maps the reflected memory region into a space that is not cacheable. Further, the apparatus includes a semaphore memory. The semaphore memory provides a hardware assist for enforced data coherency.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: July 5, 2016
    Assignee: Intel Corporation
    Inventors: Debendra Das Sharma, Mohan J. Kumar, Balint T. Fleischer
  • Publication number: 20160188414
    Abstract: Methods and apparatus to fault tolerant Automatic DIMM (Dual In-line Memory Module) Refresh or ADR are described. In an embodiment, a processor includes non-volatile memory to store data from one or more volatile buffers of the processor. The data from the one or more volatile buffers of the processor are stored into the non-volatile memory in response to occurrence of an event that is to lead to a system reset or shut down. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: December 24, 2014
    Publication date: June 30, 2016
    Applicant: Intel Corporation
    Inventors: SARATHY JAYAKUMAR, MOHAN J. KUMAR
  • Patent number: 9372752
    Abstract: An apparatus for coherent shared memory across multiple clusters is described herein. The apparatus includes a fabric memory controller and one or more nodes. The fabric memory controller manages access to a shared memory region of each node such that each shared memory region is accessible using load store semantics, even in response to failure of the node. The apparatus also includes a global memory, wherein each shared memory region is mapped to the global memory by the fabric memory controller.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: June 21, 2016
    Assignee: Intel Corporation
    Inventors: Debendra Das Sharma, Mohan J. Kumar, Balint Fleischer
  • Publication number: 20160173465
    Abstract: Technologies for verifying authorized operation includes an administration server to query a dual-headed identification device of a server for identification data indicative of an identity of the server. The dual-headed identification device includes a wired communication circuit, a wireless communication circuit, and a memory having the identification data stored therein. The administration server further obtains the identification data from the dual-headed identification device of the server, determines a context of the server, and determines whether boot of the server is authorized based on the context of the server, the identification data of the server, and a security policy of the server.
    Type: Application
    Filed: December 12, 2014
    Publication date: June 16, 2016
    Inventors: Rajesh Poornachandran, Vincent J. Zimmer, Shahrok Shahidzadeh, Mohan J. Kumar, Sergiu D. Ghetie
  • Publication number: 20160164963
    Abstract: A method, system, and device for managing hardware resources in a cloud scheduling environment includes a zone controller. The zone controller can manage groups of node servers in a cloud datacenter using a checkin service. The checkin service allows server groups to be created automatically based on one or more hardware characteristics of the node servers, server health information, workload scheduling or facilities management parameters, and/or other criteria.
    Type: Application
    Filed: December 7, 2015
    Publication date: June 9, 2016
    Inventors: Mrittika Ganguli, Mohan J. Kumar, Deepak S. Vembar, Jaiber J. John
  • Patent number: 9342394
    Abstract: Various embodiments are described herein. Some embodiments include an Operating System and a platform. The platform includes a processor having an error register. The Operating System can write to the error register only via the platform in a secure manner (for example, using platform firmware). Other embodiments are described and claimed.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: May 17, 2016
    Assignee: Intel Corporation
    Inventors: Murugasamy Nachimuthu, Mohan J. Kumar, Theodros Yigzaw, Jose A. Vargas, Rajender Kuramkote
  • Patent number: 9323539
    Abstract: Methods and apparatus related to constructing a persistent file system from scattered persistent regions are described. In one embodiment, stored information in a storage unit corresponds to one or more persistent memory regions that are scattered amongst one or more non-volatile memory devices. The one or more persistent memory regions are byte addressable. Also, the one or more persistent memory regions are used to form a virtual contiguous region. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: April 26, 2016
    Assignee: Intel Corporation
    Inventors: Anil S. Keshavamurthy, Murugasamy K. Nachimuthu, Mohan J. Kumar
  • Patent number: 9317360
    Abstract: In some implementations, a processor may include a machine check architecture having a plurality of error reporting registers able to receive data for machine check errors. A summary register may include a plurality of settable locations that each represents at least one of the error reporting registers. One or more of the settable locations in the summary register may be set to indicate whether one or more of the error reporting registers maintain data for a machine check error. Accordingly, when a machine check error occurs, the summary register may be accessed to identify if any error reporting registers in a processor's view contain valid error data, rather than having to read each of the error reporting registers in the processor's view.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: April 19, 2016
    Assignee: Intel Corporation
    Inventors: Jose A. Vargas, Mohan J. Kumar, James B. Crossland, Murugasamy K. Nachimuthu, Theodros Yigzaw
  • Patent number: 9317429
    Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: April 19, 2016
    Assignee: Intel Corporation
    Inventors: Raj K Ramanujan, Dimitrios Ziakas, David J Zimmerman, Mohan J Kumar, Muthukumar P Swaminathan, Bassam N Coury