Abstract: A process for fabricating a cavity-type integrated circuit includes supporting a leadframe strip in a mold. The leadframe strip includes a die attach pad and a row of contact pads circumscribing the die attach pad. A package body is molded in the mold such that opposing surfaces of the die attach pad and of the contact pads are exposed. A semiconductor die is mounted to the die attach pad. Various ones of the contact pads are wire bonded to the semiconductor die and a lid is mounted on the package body to thereby enclose the semiconductor die and the wire bonds in a cavity of the integrated circuit package.

Abstract: A process for fabricating an integrated circuit package includes: selectively etching a leadframe strip to define a die attach pad and at least one row of contact pads; mounting a semiconductor die to one side of the leadframe strip, on the die attach pad; wire bonding the semiconductor die to ones of the contact pads; releasably clamping the leadframe strip in a mold by releasably clamping the contact pads; molding in a molding compound to cover the semiconductor die, the wire bonds and a portion of the contact pads not covered by the clamping; releasing the leadframe strip from the mold; depositing a plurality of external contacts on the one side of the leadframe strip, on the contact pads, such that the external contacts protrude from the molding compound; mounting at least one of an active and a passive component to a second side of said leadframe strip; and singulating to provide the integrated circuit package.

Abstract: An integrated circuit package is provided. The package includes a die attach pad having a first side and a second side. A first semiconductor die is mounted to the first side of the die attach pad, a plurality of contact pads disposed in close proximity to the first semiconductor die. A first plurality of wire bonds connect the first semiconductor die and ones of the contact pads. An overmold encapsulates the first plurality of wire bonds and the first semiconductor die, the die attach pad and the contact pads being embedded in the overmold. A plurality of leads are disposed proximal the second side of the die attach pad. A second semiconductor die is mounted to one of the second side of the die attach pad and ones of the plurality of leads such that the ones of the plurality of leads are electrically connected to the second semiconductor die. The second semiconductor die and the leads are embedded in an encapsulant. The die attach pad shields the second semiconductor die.

Abstract: A process for fabricating an integrated circuit package includes mounting a semiconductor die on a first surface of a metal carrier and forming electrical connections between the semiconductor die and ones of a plurality of contacts on the metal carrier. Next, using a molding material in a mold, the semiconductor die and the contacts are molded in the molding material, between the metal carrier and a metal strip. The metal carrier and the metal strip are etched away and the integrated circuit package is singulated.

Abstract: A process for fabricating an integrated circuit package includes: selectively etching a first side of a substrate thereby providing etched regions of the substrate to partially define at least a plurality of contact pads; adding a dielectric material to the etched regions of the substrate; selectively etching a second side of the substrate to further define at least the plurality of contact pads and thereby provide a package base of at least the contact pads and the dielectric; mounting a semiconductor die to the package base and connecting the semiconductor die to the contact pads; fixing a lid to the package base to cover the semiconductor die in a cavity between the lid and the package base; and singulating to provide the integrated circuit package.

Abstract: A process for fabricating an integrated circuit package includes: selectively etching a first side of a substrate thereby providing etched regions of the substrate to partially define at least a plurality of contact pads; adding a dielectric material to the etched regions of the substrate; selectively etching a second side of the substrate to further define at least the plurality of contact pads and thereby provide a package base of at least the contact pads and the dielectric; mounting a semiconductor die to the package base and connecting the semiconductor die to the contact pads; fixing a lid to the package base to cover the semiconductor die in a cavity between the lid and the package base; and singulating to provide the integrated circuit package.

Abstract: A cavity-down ball grid includes a flexible circuit tape including a flexible tape laminated to a conductor layer. The flexible circuit tape has an aperture therein. A thermally conductive heat spreader is fixed to a first surface of the flexible circuit tape and the heat spreader has a cavity aligned with the aperture of the flexible circuit tape. A semiconductor die is mounted to the heat spreader in a die-down configuration in the cavity. A thermally conductive die adapter is fixed to the semiconductor die such that a portion of the die adapter protrudes from the cavity. A plurality of wire bonds connect the semiconductor die to bond sites on the second surface of the flexible circuit tape. An encapsulating material encapsulates the semiconductor die and the wire bonds and a plurality of solder balls are disposed on a second surface of the flexible circuit tape, in the form of a ball grid array.

Abstract: A ball grid array package is manufactured by mounting a semiconductor die to a first surface of a substrate and mounting a die adapter to the semiconductor die. The semiconductor die is wire bonded to ones of conductive traces of the substrate. A collapsible spacer is mounted to the substrate and the substrate is releasably clamped to an upper side of a mold cavity. A heat spreader and at least one collapsible spacer are placed in the mold cavity such that the collapsible spacer is disposed between the heat spreader and the substrate. A molding compound is molded in the mold, thereby molding the semiconductor die, the substrate, the wire bonds, the die adapter, the at least one collapsible spacer and the heat spreader into the molding compound to provide a molded package. A ball grid array is formed on a second surface of the substrate, bumps of the ball grid array being electrically connected to the conductive traces and the integrated circuit package is singulated.

Abstract: A ball grid array integrated circuit package is manufactured by mounting a semiconductor die, to a first surface of a substrate such that bumps on the semiconductor die are electrically connected to conductive traces of the substrate. At least one collapsible spacer is mounted to at least one of a heat spreader, the semiconductor die and the substrate. The heat spreader is fixed to the at least one of the first surface of the substrate and the semiconductor die such that the at least one collapsible spacer is disposed therebetween. A ball grid array is formed on a second surface of the substrate, bumps of the ball grid array being electrically connected to the conductive traces and the integrated circuit package is singulated.

Abstract: A process for fabricating an integrated circuit package includes: selectively etching a leadframe strip to define a die attach pad and at least one row of contact pads; mounting a semiconductor die to one side of the leadframe strip, on the die attach pad; wire bonding the semiconductor die to ones of the contact pads; releasably clamping the leadframe strip in a mold by releasably clamping the contact pads; molding in a molding compound to cover the semiconductor die, the wire bonds and a portion of the contact pads not covered by the clamping; releasing the leadframe strip from the mold; depositing a plurality of external contacts on the one side of the leadframe strip, on the contact pads, such that the external contacts protrude from the molding compound; and singulating to provide the integrated circuit package.

Abstract: A leadless plastic chip carrier is fabricated by selectively etching a leadframe strip to reduce a thickness of the strip at a portion thereof. Selectively masking the surface of the leadframe strip using a mask, follows selectively etching, to provide exposed areas of the surface at the portion and contact pad areas on leadframe the strip. At least one layer of metal is deposited on the exposed areas to define a die attach pad on the portion of the leadframe strip with reduced thickness and to define contact pads on the surface of the strip. At least one semiconductor die is mounted to the die attach pad, followed by wire bonding the at least one semiconductor die to ones of the contact pads. The at least one semiconductor die, the wire bonds, and the contact pads are covered with an overmold material and the leadframe strip is etched to thereby remove the leadframe strip. The leadless plastic chip carrier is singulated from the leadframe strip.

Abstract: An integrated circuit package is provided. The package includes a die attach pad having a first side and a second side. A first semiconductor die is mounted to the first side of the die attach pad, a plurality of contact pads disposed in close proximity to the first semiconductor die. A first plurality of wire bonds connect the first semiconductor die and ones of the contact pads. An overmold encapsulates the first plurality of wire bonds and the first semiconductor die, the die attach pad and the contact pads being embedded in the overmold. A plurality of leads are disposed proximal the second side of the die attach pad. A second semiconductor die is mounted to one of the second side of the die attach pad and ones of the plurality of leads such that the ones of the plurality of leads are electrically connected to the second semiconductor die. The second semiconductor die and the leads are embedded in an encapsulant. The die attach pad shields the second semiconductor die.

Abstract: A leadless plastic chip carrier is fabricated by partially etching at least a first surface of a leadframe strip to partially define a die attach pad, a plurality of contact pads disposed around the die attach pad, and a plurality of bond fingers intermediate the die attach pad and the contact pads. A metal strip is laminated to the first surface of the leadframe strip. A second surface of the leadframe strip is selectively etched such that portions of the leadframe strip are removed to define a remainder of the die attach pad, the plurality of contact pads, the plurality of bond fingers and circuitry between ones of the bond fingers and ones the contact pads. A semiconductor die is mounted to the die attach pad and wire bonds connect the semiconductor die to ones of the bond fingers. The second surface of the leadframe strip, the semiconductor die and the wire bonds are encapsulated in a molding material.

Abstract: A leadless plastic chip carrier is fabricated by selectively etching a leadframe strip to reduce a thickness of the strip at a portion thereof. Selectively masking the surface of the leadframe strip using a mask, follows selectively etching, to provide exposed areas of the surface at the portion and contact pad areas on leadframe the strip. At least one layer of metal is deposited on the exposed areas to define a die attach pad on the portion of the leadframe strip with reduced thickness and to define contact pads on the surface of the strip. At least one semiconductor die is mounted to the die attach pad, followed by wire bonding the at least one semiconductor die to ones of the contact pads. The at least one semiconductor die, the wire bonds, and the contact pads are covered with an overmold material and the leadframe strip is etched to thereby remove the leadframe strip. The leadless plastic chip carrier is singulated from the leadframe strip.

Abstract: A ball grid array package is manufactured by mounting a semiconductor die to a first surface of a substrate and mounting a die adapter to the semiconductor die. The semiconductor die is wire bonded to ones of conductive traces of the substrate. A collapsible spacer is mounted to the substrate and the substrate is releasably clamped to an upper side of a mold cavity. A heat spreader and at least one collapsible spacer are placed in the mold cavity such that the collapsible spacer is disposed between the heat spreader and the substrate. A molding compound is molded in the mold, thereby molding the semiconductor die, the substrate, the wire bonds, the die adapter, the at least one collapsible spacer and the heat spreader into the molding compound to provide a molded package. A ball grid array is formed on a second surface of the substrate, bumps of the ball grid array being electrically connected to the conductive traces and the integrated circuit package is singulated.

Abstract: A cavity-down ball grid includes a flexible circuit tape including a flexible tape laminated to a conductor layer. The flexible circuit tape has an aperture therein. A thermally conductive heat spreader is fixed to a first surface of the flexible circuit tape and the heat spreader has a cavity aligned with the aperture of the flexible circuit tape. A semiconductor die is mounted to the heat spreader in a die-down configuration in the cavity. A thermally conductive die adapter is fixed to the semiconductor die such that a portion of the die adapter protrudes from the cavity. A plurality of wire bonds connect the semiconductor die to bond sites on the second surface of the flexible circuit tape. An encapsulating material encapsulates the semiconductor die and the wire bonds and a plurality of solder balls are disposed on a second surface of the flexible circuit tape, in the form of a ball grid array.

Abstract: A ball grid array integrated circuit package is manufactured by mounting a semiconductor die, to a surface of a substrate such that bumps on the semiconductor die are electrically connected to conductive traces of the substrate. At least one collapsible spacer is mounted to at least one of a heat spreader, the semiconductor die and the substrate. The heat spreader is fixed to the at least one of the first surface of the substrate and the semiconductor die such that he at least one collapsible spacer is disposed therebetween. A ball grid array is formed on a second surface of the substrate, bumps of the ball grid array being electrically connected to the conductive traces and the integrated circuit package is singulated.

Abstract: A semiconductor device which receives and transmits data at high speed is tested at operational speed at wafer sort. A probe card includes a high-speed interconnect that couples probe output bonding pads to probe input bonding pads. The high-speed interconnect connects a respective output of a transmitter in the die to a respective input of a receiver in the die while the probe card is connected to the die. A built in self test circuit in the die generates test patterns and compares them for accuracy. The test patterns are routed on the high-speed interconnect from the output of the transmitter to the input of the receiver allowing the data path through the receiver and transmitter in the die to be tested at operational speed before the die is assembled into a package.

Abstract: A semiconductor device which receives and transmits data at high speed is tested at operational speed at wafer sort. A probe card includes a high-speed interconnect that couples probe output bonding pads to probe input bonding pads. The high-speed interconnect connects a respective output of a transmitter in the die to a respective input of a receiver in the die while the probe card is connected to the die. A built in self test circuit in the die generates test patterns and compares them for accuracy. The test patterns are routed on the high-speed interconnect from the output of the transmitter to the input of the receiver allowing the data path through the receiver and transmitter in the die to be tested at operational speed before the die is assembled into a package.

Abstract: A semiconductor device is provided which improves reliability by preventing connection defects with extensions and interface peeling occurring between a substrate and a sealing resin, and which can reduce the production cost by simplifying a fabrication process. In this semiconductor device, each lead 16 for electrically connecting an electrode terminal 12 of a semiconductor chip to an external connection terminal 14 comprises an extension 17 extending parallel to an electrode terminal formation surface of the semiconductor chip 10 with a predetermined distance from the electrode terminal formation surface, an external connection terminal post 22 provided to one of the end portions of the extension 17, and an electrode terminal post 24 connected to the electrode terminal 12 of the semiconductor chip 10. The electrode terminal post 22 and the extension 17 are sealed by a sealing resin 18, and the distal end portion of the external connection terminal post 24 is exposed from the sealing resin 18.