Patents by Inventor Mohd Kamran Akhtar
Mohd Kamran Akhtar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200243537Abstract: Methods, apparatuses, and systems related to forming a trench using a polymerizing radical material. An example method includes depositing a polymerizing radical material in a number of trenches formed over a substrate. The method further includes etching a portion of the deposited polymerizing radical material from the number of trenches. The example method further includes selectively etching into one of the number of trenches below the deposited polymerizing radical material. The one of the number of trenches is narrower than another of the number of trenches.Type: ApplicationFiled: January 28, 2019Publication date: July 30, 2020Inventors: Yan Li, Song Guo, Mohd Kamran Akhtar, Alex J. Schrinsky
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Patent number: 10707215Abstract: A semiconductor device comprises semiconductive pillars; digit lines laterally between the semiconductive pillars; nitride caps vertically overlying the digit lines; nitride structures overlying surfaces of the nitride caps; redistribution material structures comprising upper portions overlying upper surfaces of the nitride caps and the nitride structures, and lower portions overlying upper surfaces of the semiconductive pillars; a low-K dielectric material laterally between the digit lines and the semiconductive pillars; air gaps laterally between the low-K dielectric material and the semiconductive pillars, and having upper boundaries below the upper surfaces of the nitride caps; and a nitride dielectric material laterally between the air gaps and the semiconductive pillars. Memory devices, electronic systems, and method of forming a semiconductor device are also described.Type: GrantFiled: August 22, 2018Date of Patent: July 7, 2020Assignee: Micron Technology, Inc.Inventors: Arzum F. Simsek-Ege, Guangjun Yang, Kuo-Chen Wang, Mohd Kamran Akhtar, Katsumi Koge
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Patent number: 10700073Abstract: Some embodiments include a method of forming an integrated assembly. A construction is formed to include a conductive structure having a top surface, and a pair of sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface, and rails are along the sidewall surfaces. The rails include sacrificial material. The sacrificial material is removed to leave openings. Sealant material is formed to extend within the openings. The sealant material has a lower dielectric constant than the insulative material. Some embodiments include an integrated assembly having a conductive structure with a top surface and a pair of opposing sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface. Voids are along the sidewall surfaces and are capped by sealant material. The sealant material has a lower dielectric constant than the insulative material.Type: GrantFiled: May 22, 2019Date of Patent: June 30, 2020Assignee: Micron Technology, Inc.Inventors: Guangjun Yang, Mohd Kamran Akhtar, Silvia Borsari, Alex J. Schrinsky
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Patent number: 10665665Abstract: Systems, apparatuses, and methods related to passivation material for a pillar adjacent a trench are described. An example method includes forming a passivation material on a top region of a pillar adjacent a trench of a semiconductor device and removing a first portion of the passivation material to form, on a remaining second portion of the passivation material, a surface that is coplanar with an underlying sidewall of the pillar. The example method further includes removing a portion of a substrate material at a bottom region of the trench and removing the remaining second portion of the passivation material from the top region.Type: GrantFiled: October 22, 2018Date of Patent: May 26, 2020Inventors: Guangjun Yang, Mohd Kamran Akhtar
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Publication number: 20200127080Abstract: Systems, apparatuses, and methods related to passivation material for a pillar adjacent a trench are described. An example method includes forming a passivation material on a top region of a pillar adjacent a trench of a semiconductor device and removing a first portion of the passivation material to form, on a remaining second portion of the passivation material, a surface that is coplanar with an underlying sidewall of the pillar. The example method further includes removing a portion of a substrate material at a bottom region of the trench and removing the remaining second portion of the passivation material from the top region.Type: ApplicationFiled: October 22, 2018Publication date: April 23, 2020Inventors: Guangjun Yang, Mohd Kamran Akhtar
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Publication number: 20200118919Abstract: A method of forming a semiconductor device structure comprises forming a stack structure over a substrate, the stack structure comprising tiers each independently comprising a sacrificial structure and an insulating structure and longitudinally adjacent the sacrificial structure. A masking structure is formed over a portion of the stack structure. A photoresist is formed over the masking structure and over additional portions of the stack structure not covered by the masking structure. The photoresist and the stack structure are subjected to a series of material removal processes to selectively remove portions of the photoresist and portions of the stack structure not covered by one or more of the masking structure and remaining portions of the photoresist to form a stair step structure. Semiconductor devices and additional methods of forming a semiconductor device structure are also described.Type: ApplicationFiled: November 7, 2019Publication date: April 16, 2020Inventors: Troy R. Sorensen, Mohd Kamran Akhtar
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Publication number: 20200066729Abstract: A semiconductor device comprises semiconductive pillars; digit lines laterally between the semiconductive pillars; nitride caps vertically overlying the digit lines; nitride structures overlying surfaces of the nitride caps; redistribution material structures comprising upper portions overlying upper surfaces of the nitride caps and the nitride structures, and lower portions overlying upper surfaces of the semiconductive pillars; a low-K dielectric material laterally between the digit lines and the semiconductive pillars; air gaps laterally between the low-K dielectric material and the semiconductive pillars, and having upper boundaries below the upper surfaces of the nitride caps; and a nitride dielectric material laterally between the air gaps and the semiconductive pillars. Memory devices, electronic systems, and method of forming a semiconductor device are also described.Type: ApplicationFiled: August 22, 2018Publication date: February 27, 2020Inventors: Arzum F. Simsek-Ege, Guangjun Yang, Kuo-Chen Wang, Mohd Kamran Akhtar, Katsumi Koge
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Publication number: 20200058663Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: October 24, 2019Publication date: February 20, 2020Applicant: Micron Technology, Inc.Inventors: Justin B. Dorhout, Kunal R. Parekh, Martin C. Roberts, Mohd Kamran Akhtar, Chet E. Carter, David Daycock
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Publication number: 20190378843Abstract: Some embodiments include a method of forming an integrated assembly. A construction is formed to include a conductive structure having a top surface, and a pair of sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface, and rails are along the sidewall surfaces. The rails include sacrificial material. The sacrificial material is removed to leave openings. Sealant material is formed to extend within the openings. The sealant material has a lower dielectric constant than the insulative material. Some embodiments include an integrated assembly having a conductive structure with a top surface and a pair of opposing sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface. Voids are along the sidewall surfaces and are capped by sealant material. The sealant material has a lower dielectric constant than the insulative material.Type: ApplicationFiled: May 22, 2019Publication date: December 12, 2019Applicant: Micron Technology, Inc.Inventors: Guangjun Yang, Mohd Kamran Akhtar, Silvia Borsari, Alex J. Schrinsky
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Patent number: 10483270Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: February 7, 2019Date of Patent: November 19, 2019Assignee: Micron Technology, Inc.Inventors: Justin B. Dorhout, Kunal R. Parekh, Martin C. Roberts, Mohd Kamran Akhtar, Chet E. Carter, David Daycock
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Patent number: 10347643Abstract: Some embodiments include a method of forming an integrated assembly. A construction is formed to include a conductive structure having a top surface, and a pair of sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface, and rails are along the sidewall surfaces. The rails include sacrificial material. The sacrificial material is removed to leave openings. Sealant material is formed to extend within the openings. The sealant material has a lower dielectric constant than the insulative material. Some embodiments include an integrated assembly having a conductive structure with a top surface and a pair of opposing sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface. Voids are along the sidewall surfaces and are capped by sealant material. The sealant material has a lower dielectric constant than the insulative material.Type: GrantFiled: June 7, 2018Date of Patent: July 9, 2019Assignee: Micron Technology, Inc.Inventors: Guangjun Yang, Mohd Kamran Akhtar, Silvia Borsari, Alex J. Schrinsky
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Publication number: 20190206883Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: February 7, 2019Publication date: July 4, 2019Applicant: Micron Technology, Inc.Inventors: Justin B. Dorhout, Kunal R. Parekh, Martin C. Roberts, Mohd Kamran Akhtar, Chet E. Carter, David Daycock
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Patent number: 10229923Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: November 20, 2017Date of Patent: March 12, 2019Assignee: Micron Technology, Inc.Inventors: Justin B. Dorhout, Kunal R. Parekh, Martin C. Roberts, Mohd Kamran Akhtar, Chet E. Carter, David Daycock
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Patent number: 9984977Abstract: Some embodiments include a construction having conductive structures spaced from one another by intervening regions. Insulative structures are within the intervening regions. The insulative structures include dielectric spacers and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps. The dielectric capping material is between the dielectric spacers and not over upper surfaces of the dielectric spacers. Some embodiments include a construction having a first conductive structure with an upper surface, and having a plurality of second conductive structures electrically coupled with the upper surface of the first conductive structure and spaced from one another by intervening regions. Air gap/spacer insulative structures are within the intervening regions. The air gap/spacer insulative structures have dielectric spacers along sidewalls of the second conductive structures and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps.Type: GrantFiled: May 22, 2017Date of Patent: May 29, 2018Assignee: Micron Technology, Inc.Inventors: Ashim Dutta, Mohd Kamran Akhtar, Shane J. Trapp
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Publication number: 20180082940Abstract: A method of forming a semiconductor device structure comprises forming a stack structure over a substrate, the stack structure comprising tiers each independently comprising a sacrificial structure and an insulating structure and longitudinally adjacent the sacrificial structure. A masking structure is formed over a portion of the stack structure. A photoresist is formed over the masking structure and over additional portions of the stack structure not covered by the masking structure. The photoresist and the stack structure are subjected to a series of material removal processes to selectively remove portions of the photoresist and portions of the stack structure not covered by one or more of the masking structure and remaining portions of the photoresist to form a stair step structure. Semiconductor devices and additional methods of forming a semiconductor device structure are also described.Type: ApplicationFiled: September 21, 2016Publication date: March 22, 2018Inventors: Troy R. Sorensen, Mohd Kamran Akhtar
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Publication number: 20180076209Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region are majority doped with a same dopant type. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending across a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends outwardly from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: November 20, 2017Publication date: March 15, 2018Applicant: Micron Technology, Inc.Inventors: Justin B. Dorhout, Kunal R. Parekh, Martin C. Roberts, Mohd Kamran Akhtar, Chet E. Carter, David Daycock
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Patent number: 9853037Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have majority carriers of the same conductivity type. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: November 23, 2015Date of Patent: December 26, 2017Assignee: Micron Technology, Inc.Inventors: Justin B. Dorhout, Kunal R. Parekh, Martin C. Roberts, Mohd Kamran Akhtar, Chet E. Carter, David Daycock
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Publication number: 20170263563Abstract: Some embodiments include a construction having conductive structures spaced from one another by intervening regions. Insulative structures are within the intervening regions. The insulative structures include dielectric spacers and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps. The dielectric capping material is between the dielectric spacers and not over upper surfaces of the dielectric spacers. Some embodiments include a construction having a first conductive structure with an upper surface, and having a plurality of second conductive structures electrically coupled with the upper surface of the first conductive structure and spaced from one another by intervening regions. Air gap/spacer insulative structures are within the intervening regions. The air gap/spacer insulative structures have dielectric spacers along sidewalls of the second conductive structures and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps.Type: ApplicationFiled: May 22, 2017Publication date: September 14, 2017Applicant: Micron Technology, Inc.Inventors: Ashim Dutta, Mohd Kamran Akhtar, Shane J. Trapp
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Patent number: 9679852Abstract: Some embodiments include a construction having conductive structures spaced from one another by intervening regions. Insulative structures are within the intervening regions. The insulative structures include dielectric spacers and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps. The dielectric capping material is between the dielectric spacers and not over upper surfaces of the dielectric spacers. Some embodiments include a construction having a first conductive structure with an upper surface, and having a plurality of second conductive structures electrically coupled with the upper surface of the first conductive structure and spaced from one another by intervening regions. Air gap/spacer insulative structures are within the intervening regions. The air gap/spacer insulative structures have dielectric spacers along sidewalls of the second conductive structures and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps.Type: GrantFiled: July 1, 2014Date of Patent: June 13, 2017Assignee: Micron Technology, Inc.Inventors: Ashim Dutta, Mohd Kamran Akhtar, Shane J. Trapp
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Publication number: 20170148802Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: November 23, 2015Publication date: May 25, 2017Inventors: Justin B. Dorhout, Kunal R. Parekh, Martin C. Roberts, Mohd Kamran Akhtar, Chet E. Carter, David Daycock