Patents by Inventor Mohit K. Prasad

Mohit K. Prasad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9119222
    Abstract: Methods, systems, and devices are described for providing a reconfigurable multi-chip WWAN processing platform on a communications device. The processing platform allows the device to access multiple WWANs and multiple WWAN technologies concurrently. A first multiplexer is communicatively coupled with a number of baseband processing chips. A first baseband processing chip is selectively coupled with a first transceiver and a first UICC module to establish a first connection. A second baseband processing chip is selectively coupled with a second transceiver and a second UICC module to establish a second connection operable concurrently with the first connection. A multiplexer controller performs a configurable search for available networks. One or more networks are selected. The controller selects a specific transceiver for each selected network based on the capabilities of the transceiver.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: August 25, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Dilip Krishnaswamy, Irfan H. Khan, Samir S. Soliman, Mohit K. Prasad
  • Patent number: 8621322
    Abstract: Methods and corresponding systems in an interleaver include loading K symbol data, in a linear order, into a matrix memory having (R·C) storage locations corresponding R rows and C columns. A sequence of interleaved addresses is produced for reading the K symbol data in an interleaved order from the matrix memory. Next, (R·C)?K interleaved addresses are queued in a first-in-first-out (FIFO) memory. After queuing (R·C)?K interleaved addresses in the FIFO memory, symbol data is output using the interleaved addresses in the FIFO memory to address and output the symbol data in the matrix memory in the interleaved order. The FIFO memory can contain at least 234 memory locations.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: December 31, 2013
    Assignee: FreeScale Semiconductor, Inc.
    Inventors: Mohit K. Prasad, Clark H. Jarvis
  • Patent number: 8621122
    Abstract: One embodiment of the invention comprises a non-transitory, tangible computer readable storage medium encoded with processor readable instructions to perform a method of transferring SDIO data. One method comprises buffering multiple IP packets to transfer from one of a SDCC host and a SDIO client to the other of the SDCC host and the SDIO client. A multiplexing header is attached to each of the multiple IP packets and one of at least one SDIO read command and at least one SDIO write command issued. The multiple IP packets are then transferred in a single SDIO transfer between the one of a SDCC host and a SDIO client to the other of the SDCC host and the SDIO client.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: December 31, 2013
    Assignee: Qualcomm Innovation Center, Inc.
    Inventors: Vaibhav Kumar, Mark A. Landguth, Mohit K. Prasad, Erez Tsidon, Shailesh Maheshwari, Rashmi Char, Robert C. Coleman
  • Publication number: 20130058216
    Abstract: Methods, systems, and devices are described for providing a reconfigurable multi-chip WWAN processing platform on a communications device. The processing platform allows the device to access multiple WWANs and multiple WWAN technologies concurrently. A first multiplexer is communicatively coupled with a number of baseband processing chips. A first baseband processing chip is selectively coupled with a first transceiver and a first UICC module to establish a first connection. A second baseband processing chip is selectively coupled with a second transceiver and a second UICC module to establish a second connection operable concurrently with the first connection. A multiplexer controller performs a configurable search for available networks. One or more networks are selected. The controller selects a specific transceiver for each selected network based on the capabilities of the transceiver.
    Type: Application
    Filed: September 1, 2011
    Publication date: March 7, 2013
    Applicant: QUALCOMM Incorporated
    Inventors: Dilip Krishnaswamy, Irfan H. Khan, Samir S. Soliman, Mohit K. Prasad
  • Publication number: 20120260008
    Abstract: One embodiment of the invention comprises a non-transitory, tangible computer readable storage medium encoded with processor readable instructions to perform a method of transferring SDIO data. One method comprises buffering multiple IP packets to transfer from one of a SDCC host and a SDIO client to the other of the SDCC host and the SDIO client. A multiplexing header is attached to each of the multiple IP packets and one of at least one SDIO read command and at least one SDIO write command issued. The multiple IP packets are then transferred in a single SDIO transfer between the one of a SDCC host and a SDIO client to the other of the SDCC host and the SDIO client.
    Type: Application
    Filed: April 7, 2011
    Publication date: October 11, 2012
    Applicant: QUALCOMM INNOVATION CENTER, INC.
    Inventors: Vaibhav Kumar, Mark A. Landguth, Mohit K. Prasad, Erez Tsidon, Shailesh Maheshwari, Rashmi Char, Robert C. Coleman
  • Publication number: 20100083072
    Abstract: Methods and corresponding systems in an interleaver include loading K symbol data, in a linear order, into a matrix memory having (R·C) storage locations corresponding R rows and C columns. A sequence of interleaved addresses is produced for reading the K symbol data in an interleaved order from the matrix memory. Next, (R·C)?K interleaved addresses are queued in a first-in-first-out (FIFO) memory. After queuing (R·C)?K interleaved addresses in the FIFO memory, symbol data is output using the interleaved addresses in the FIFO memory to address and output the symbol data in the matrix memory in the interleaved order. The FIFO memory can contain at least 234 memory locations.
    Type: Application
    Filed: September 30, 2008
    Publication date: April 1, 2010
    Inventors: Mohit K. Prasad, Clark H. Jarvis
  • Patent number: 7404139
    Abstract: A Maximum Likelihood Sequence Estimation (MLSE) decoder that decodes an encoded sequence of data symbols includes a branch metric unit for computing branch metrics for each trellis stage of the encoded sequence, a path metric unit for computing a path metric for each trellis stage using the computed branch metrics, and an M-at-a-time traceback unit for performing an M-at-a-time traceback operation using the computed path metrics. The M-at-a-time traceback operation generates M decoded data symbols in a single M-at-a-time traceback operation.
    Type: Grant
    Filed: January 21, 2005
    Date of Patent: July 22, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mohit K. Prasad, Nitin Vig, Arnab K. Mitra, Amrit P. Singh, Gaurav Davra
  • Patent number: 7231586
    Abstract: A method and system for decoding a data symbol sequence that has been previously encoded using one or more unique code word polynomials in which at least one unique code word polynomial is used more than once. A set of 2d-1 unique branch metrics is computed, using the unique code word polynomials, where d is the number of unique code word polynomials. The computed set of 2d-1 unique branch metrics is stored in a memory. Path metrics are then calculated, based on the stored set of 2d-1 unique branch metrics. A decoded data symbol sequence is generated based on the computed path metrics.
    Type: Grant
    Filed: July 21, 2004
    Date of Patent: June 12, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mohit K. Prasad, Gaurav Davra, Arnab K. Mitra, Amrit P. Singh, Nitin Vig
  • Patent number: 6788728
    Abstract: A reverse link modulator modulates the incoming data sequence for the I and Q channels of a wireless device such that the resulting spreading sequence never undergoes a transition through the origin. Consequently, the modulator has a reduced peak-to-average ratio and provides an improved battery life.
    Type: Grant
    Filed: January 5, 2000
    Date of Patent: September 7, 2004
    Assignees: Sony Corporation, Sony Electronics, Inc.
    Inventors: Mohit K. Prasad, Sam Heidari
  • Patent number: 6748561
    Abstract: A method and apparatus is provided for interleaving and de-interleaving frame symbols using a single memory buffer. Input frame symbols are read out in an interleaved sequence (or de-interleaved sequence) on a symbol by symbol basis. Frame symbols following the input frame symbols are written into memory locations from where the input frame symbols were read.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: June 8, 2004
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventor: Mohit K. Prasad
  • Publication number: 20030163776
    Abstract: A method and apparatus is provided for interleaving and de-interleaving frame symbols using a single memory buffer. Input frame symbols are read out in an interleaved sequence (or de-interleaved sequence) on a symbol by symbol basis. Frame symbols following the input frame symbols are written into memory locations from where the input frame symbols were read.
    Type: Application
    Filed: December 20, 2002
    Publication date: August 28, 2003
    Inventor: Mohit K. Prasad
  • Patent number: 6560212
    Abstract: An offset sequence generator generates an offset sequence from a reference sequence, the offset sequence being a cyclic-shifted version of the reference sequence. The reference sequence is a deBruijn sequence formed from a pseudo-noise (PN) sequence augmented with an insert-bit, the insert-bit being inserted at a rollover state of the PN sequence. The offset generator includes a decision circuit that selects values of either the reference sequence or a delayed reference sequence as an input to a mask circuit. The mask circuit applies masks so as to generate the PN sequence of the offset sequence. The decision circuit also detects the rollover state of the PN sequence of the offset sequence, and inserts the insert-bit so as to provide the offset sequence.
    Type: Grant
    Filed: March 16, 1999
    Date of Patent: May 6, 2003
    Assignee: Agere Systems Inc.
    Inventors: Mohit K. Prasad, Xiao-An Wang
  • Patent number: 6553517
    Abstract: A method and apparatus is provided for interleaving and de-interleaving frame symbols using a single memory buffer. Input frame symbols are read out in an interleaved sequence (or de-interleaved sequence) on a symbol by symbol basis. Frame symbols following the input frame symbols are written into memory locations from where the input frame symbols were read.
    Type: Grant
    Filed: April 7, 2000
    Date of Patent: April 22, 2003
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventor: Mohit K. Prasad
  • Patent number: 6377618
    Abstract: Rate detection of a data rate within a sequence of transmitted symbols employs correlation to calculate estimates of the auto-correlation values, or estimated coefficients, of the sequence. When the sequence of transmitted symbols includes repeated symbol values, the auto-correlation values indicate a degree of self-similarity within the sequence. A decision statistic may be formed from the auto-correlation values. The self-similarity of the auto-correlation values may be employed as a decision statistic with associated hypothesis test pair values. Various decision methods may be implemented to compare auto-correlation values to thresholds based on the hypothesis test pair values. Based on the comparison, the data rate of the sequence may be determined. Once the information is determined related to the data rate, the information may be employed by a Viterbi detector to adjust the decoding rate for decoding the symbols.
    Type: Grant
    Filed: December 30, 1998
    Date of Patent: April 23, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Mohit K. Prasad, Mark E. Warner
  • Patent number: 6324205
    Abstract: A scalable method and system for generating a 3X long code sequence for use in a CDMA communication system uses Gold sequences. A preferred pair of 1X long code sequences both running at 1.2288 Mchips/s are used to generate the 3X sequence. The 3X sequence so generated is a pseudo-random sequence with well defined auto-correlation and cross-correlation properties. Because the method is scalable it is easily scaled to generate other long code e.g. 6X, 9X, and 12X sequences.
    Type: Grant
    Filed: May 9, 2000
    Date of Patent: November 27, 2001
    Assignees: Sony Corporation, Sony Electronics, Inc.
    Inventor: Mohit K. Prasad
  • Patent number: 6295287
    Abstract: Interleaving of reverse-link channels is performed by implementing closed-form expressions that are equivalent to the table-based processing specified in the cdmaOne telecommunication specification. The implementation can be in either hardware or software or a combination of both. For each cdmaOne reverse-link channel, the closed-form expression relates each un-interleaved symbol position to a corresponding interleaved symbol position, which is used to generate an interleaved symbol stream from the un-interleaved symbol stream. In one hardware implementation, the reverse-link interleaver of the present invention has an address generation unit made from a modulo counter, five muxes, a multiplier, and an adder.
    Type: Grant
    Filed: March 13, 1998
    Date of Patent: September 25, 2001
    Assignee: Agere System Guardian Corp.
    Inventor: Mohit K. Prasad
  • Patent number: 6198732
    Abstract: Interleaving of forward-link paging or traffic channels is performed by implementing closed-form expressions that are equivalent to the table-based processing specified in the cdmaOne telecommunication specification. The implementation can be in either hardware or software or a combination of both. For each cdmaOne forward-link paging or traffic channel, the closed-form expression relates each un-interleaved symbol position to a corresponding interleaved symbol position, which is used to generate an interleaved symbol stream from the un-interleaved symbol stream. In one hardware implementation, the forward-link interleaver of the present invention has an address generation unit made from a modulo counter, a multiplier, and an adder.
    Type: Grant
    Filed: March 13, 1998
    Date of Patent: March 6, 2001
    Assignee: Lucent Technologies Inc.
    Inventor: Mohit K. Prasad
  • Patent number: 6198733
    Abstract: Interleaving and de-interleaving of forward-link Sync channels is performed by implementing closed-form expressions that are equivalent to the table-based processing specified in the cdmaOne telecommunication specification. The implementation can be in either hardware or software or a combination of both. For Sync-channel interleaving, the closed-form expression relates each un-interleaved symbol position to a corresponding interleaved symbol position, which is used to generate an interleaved symbol stream from the un-interleaved symbol stream. For Sync-channel de-interleaving, the closed-form expression relates each interleaved symbol position to a corresponding de-interleaved symbol position, which is used to generate a de-interleaved symbol stream from the interleaved symbol stream. In one hardware implementation, the forward-link interleaver/de-interleaver of the present invention has an address generation unit made from a modulo counter and a bit reversal unit.
    Type: Grant
    Filed: March 13, 1998
    Date of Patent: March 6, 2001
    Assignee: Lucent Technologies Inc.
    Inventor: Mohit K. Prasad
  • Patent number: 6195344
    Abstract: De-interleaving of forward-link paging or traffic channels is performed by implementing closed-form expressions that are equivalent to the table-based processing specified in the cdmaOne telecommunication specification. The implementation can be in either hardware or software or a combination of both. For each cdmaOne forward-link paging or traffic channel, the closed-form expression relates each interleaved symbol position to a corresponding de-interleaved symbol position, which is used to generate a de-interleaved symbol stream from the interleaved symbol stream. In one hardware implementation, the forward-link de-interleaver of the present invention has an address generation unit made from two modulo counters.
    Type: Grant
    Filed: March 13, 1998
    Date of Patent: February 27, 2001
    Assignee: Lucent Technologies Inc.
    Inventor: Mohit K. Prasad
  • Patent number: 6185200
    Abstract: De-interleaving of reverse-link channels is performed by implementing closed-form expressions that are equivalent to the table-based processing specified in the cdmaOne telecommunication specification. The implementation can be in either hardware or software or a combination of both For each cdmaOne reverse-link channel, the closed-form expression relates each interleaved symbol position to a corresponding de-interleaved symbol position, which is used to generate a de-interleaved symbol stream from the interleaved symbol stream. In one hardware implementation, the reverse-link de-interleaver of the present invention has an address generation unit made from two modulo counters and five muxes.
    Type: Grant
    Filed: March 13, 1998
    Date of Patent: February 6, 2001
    Assignee: Lucent Technologies Inc.
    Inventor: Mohit K. Prasad