Abstract: A prober head to interface an E-testing apparatus to a device under test, which may be an unpackaged die, for example. In some embodiments, the prober head includes an array of conductive pins, each of the pins extending outwardly from a first pin end anchored to a substrate. At least a partial length of each of the pins is coated with a hydrophobic monolayer. The conductive pins may be composite metal wires including a core metal encased by one or more peripheral metal. At a tip of the pins, opposite the first pin end anchored to the substrate, the peripheral metals are recessed from the core metal. In further embodiments, the hydrophobic monolayer is disposed on an outer surface of the peripheral metals, but is substantially absent from a surface of the core metal exposed at the tip.

Abstract: An apparatus is provided which comprises: a substrate to couple with one or more integrated circuit die(s), an integrated circuit die coupled to the substrate, a metal component coupled to the substrate, wherein the metal component lacks a sealing coating, and a sacrificial metal conductively coupled with the metal component, wherein the sacrificial metal comprises a more anodic metal than the metal component. Other embodiments are also disclosed and claimed.

Abstract: Disclosed herein are integrated circuit (IC) packages with an electronic component having a patterned protective material on a face, as well as related devices and methods. In some embodiments, a computing device may include: an integrated circuit (IC) package with an electronic component having a protective material on the back face of the electronic component, where the protective material is patterned to include an area on the back face of the electronic component that is not covered by the protective material; a circuit board, where the IC package is electrically coupled to the circuit board; and a heat spreader, where the heat spreader is secured to the circuit board and in thermal contact with the area on the back face of the electronic component that is not covered by the protective material.

Abstract: Disclosed herein are integrated circuit (IC) packages with an electronic component having a patterned protective material on a face, as well as related devices and methods. In some embodiments, a computing device may include: an integrated circuit (IC) package with an electronic component having a protective material on the back face of the electronic component, where the protective material is patterned to include an area on the back face of the electronic component that is not covered by the protective material; a circuit board, where the IC package is electrically coupled to the circuit board; and a heat spreader, where the heat spreader is secured to the circuit board and in thermal contact with the area on the back face of the electronic component that is not covered by the protective material.

Abstract: A prober head to interface an E-testing apparatus to a device under test, which may be an unpackaged die, for example. In some embodiments, the prober head includes an array of conductive pins, each of the pins extending outwardly from a first pin end anchored to a substrate. At least a partial length of each of the pins is coated with a hydrophobic monolayer. The conductive pins may be composite metal wires including a core metal encased by one or more peripheral metal. At a tip of the pins, opposite the first pin end anchored to the substrate, the peripheral metals are recessed from the core metal. In further embodiments, the hydrophobic monolayer is disposed on an outer surface of the peripheral metals, but is substantially absent from a surface of the core metal exposed at the tip.

Abstract: A prober head to interface an E-testing apparatus to a device under test, which may be an unpackaged die, for example. In some embodiments, the prober head includes an array of conductive pins, each of the pins extending outwardly from a first pin end anchored to a substrate. At least a partial length of each of the pins is coated with a hydrophobic monolayer. The conductive pins may be composite metal wires including a core metal encased by one or more peripheral metal. At a tip of the pins, opposite the first pin end anchored to the substrate, the peripheral metals are recessed from the core metal. In further embodiments, the hydrophobic monolayer is disposed on an outer surface of the peripheral metals, but is substantially absent from a surface of the core metal exposed at the tip.

Abstract: An apparatus is provided which comprises: a substrate to couple with one or more integrated circuit die(s), an integrated circuit die coupled to the substrate, a metal component coupled to the substrate, wherein the metal component lacks a sealing coating, and a sacrificial metal conductively coupled with the metal component, wherein the sacrificial metal comprises a more anodic metal than the metal component. Other embodiments are also disclosed and claimed.

Abstract: A thermal heat for integrated circuit die processing is described that includes a thermal barrier. In one example, the thermal head has a ceramic heater configured to carry an integrated circuit die, a metal base, and a thermal barrier between the heater and the base.

Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package including a die on a substrate, where the die has a front side surface electrically coupled to the substrate and a backside surface that is opposite from the front side surface. The semiconductor package also has a bicontinuous ceramic composite (BCC) stiffener on the backside surface of the die. The BCC stiffener may include one or more materials, including porous ceramics, polymeric resins, and metals. The BCC stiffener may be directly coupled to the backside surface of the die without an adhesive layer. The BCC stiffener may be disposed on the die to reduce warpage based on the substrate and die. The semiconductor package may have the BCC stiffener formed with the one or more materials using a polymeric resin in a liquid state process and a resin pre-loaded in a ceramic process.

Abstract: Some example forms relate to a stiffener tape for a wafer. The stiffener tape includes a mounting tape and a stiffener removably attached to the mounting tape. The stiffener tape further includes a die attach film attached to the stiffener. Other example forms relate to an electronic assembly that includes a wafer and a stiffener tape attached to the wafer. The stiffener tape includes a die attach film mounted to the wafer. A stiffener is attached to the die attach film and a mounting tape is removably attached to the stiffener. Still other example forms relate to a method that includes forming a stiffener tape which includes a mounting tape, a stiffener removably attached to the mounting tape and a die attach film attached to the stiffener.

Abstract: A prober head to interface an E-testing apparatus to a device under test, which may be an unpackaged die, for example. In some embodiments, the prober head includes an array of conductive pins, each of the pins extending outwardly from a first pin end anchored to a substrate. At least a partial length of each of the pins is coated with a hydrophobic monolayer. The conductive pins may be composite metal wires including a core metal encased by one or more peripheral metal. At a tip of the pins, opposite the first pin end anchored to the substrate, the peripheral metals are recessed from the core metal. In further embodiments, the hydrophobic monolayer is disposed on an outer surface of the peripheral metals, but is substantially absent from a surface of the core metal exposed at the tip.

Abstract: Techniques and mechanisms to mitigate contamination of redistribution layer structures disposed on a back side of a semiconductor substrate. In an embodiment, a microelectronics device includes a substrate and integrated circuitry variously formed in or on a front side of the substrate, where vias extend from the integrated circuitry to a back side of the substrate. A redistribution layer disposed on the back side includes a ring structure and a plurality of raised structures each extending from a recess portion that is surrounded by the ring structure. The ring structure and the plurality of raised structures provide contact surfaces for improved adhesion of dicing tape to the back side. In another embodiment, the plurality of raised structures includes dummification comprising dummy structures that are each electrically decoupled from any via extending through the substrate.

Abstract: Techniques and mechanisms to mitigate contamination of redistribution layer structures disposed on a back side of a semiconductor substrate. In an embodiment, a microelectronics device includes a substrate and integrated circuitry variously formed in or on a front side of the substrate, where vias extend from the integrated circuitry to a back side of the substrate. A redistribution layer disposed on the back side includes a ring structure and a plurality of raised structures each extending from a recess portion that is surrounded by the ring structure. The ring structure and the plurality of raised structures provide contact surfaces for improved adhesion of dicing tape to the back side. In another embodiment, the plurality of raised structures includes dummification comprising dummy structures that are each electrically decoupled from any via extending through the substrate.

Abstract: A thermal heat for integrated circuit die processing is described that includes a thermal barrier. In one example, the thermal head has a ceramic heater configured to carry an integrated circuit die, a metal base, and a thermal barrier between the heater and the base.

Abstract: Described is an apparatus which comprises a wafer tray having an adhesive layer, with dynamically adjustable adhesion properties, deposited on a surface of the wafer tray; a wafer positioned on the wafer tray; and a cooling agent which is operable to cool at least a portion of the adhesive layer below its glass transition temperature (Tg) such that the wafer can be lifted off the wafer tray. Described is an apparatus which comprises: a tape having an adhesive layer, the adhesive layer having dynamically adjustable adhesion properties; a chip package to be attached to the tape via the adhesive layer; and a cooling agent which is operable to cool at least a portion of the adhesive layer below its Tg such that the chip package can be lifted off the tape.

Abstract: An apparatus includes a coreless substrate with a through-silicon via (TSV) embedded die that is integral to the coreless substrate. The apparatus includes a subsequent die that is coupled to the TSV die and that is disposed above the coreless substrate.

Abstract: Some example forms relate to a stiffener tape for a wafer. The stiffener tape includes a mounting tape and a stiffener removably attached to the mounting tape. The stiffener tape further includes a die attach film attached to the stiffener. Other example forms relate to an electronic assembly that includes a wafer and a stiffener tape attached to the wafer. The stiffener tape includes a die attach film mounted to the wafer. A stiffener is attached to the die attach film and a mounting tape is removably attached to the stiffener. Still other example forms relate to a method that includes forming a stiffener tape which includes a mounting tape, a stiffener removably attached to the mounting tape and a die attach film attached to the stiffener.

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a patterned die backside film (DBF) on a backside of a die, wherein the patterned DBF comprises an opening surrounding at least one through silicon via (TSV) pad disposed on the backside of the die.

Abstract: An apparatus includes a coreless substrate with a through-silicon via (TSV) embedded die that is integral to the coreless substrate. The apparatus includes a subsequent die that is coupled to the TSV die and that is disposed above the coreless substrate.

Abstract: An apparatus includes a coreless substrate with a through-silicon via (TSV) embedded die that is integral to the coreless substrate. The apparatus includes a subsequent die that is coupled to the TSV die and that is disposed above the coreless substrate.