Patents by Inventor Mohsen Alavi
Mohsen Alavi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7280425Abstract: A one-time programmable (OTP) cell includes an access transistor coupled to an antifuse transistor. Access transistor has a gate oxide thickness that is greater than the gate oxide thickness of the antifuse transistor so that if the antifuse transistor is programmed, the voltage felt across the gate/drain junction of the access transistor is insufficient to cause the gate oxide of the access transistor to break down. The dual gate oxide OTP cell may be used in an array in which only one OTP cell is programmed at a time. The dual gate oxide OTP cell also may be used in an array in which several OTP cells are programmed simultaneously.Type: GrantFiled: September 30, 2005Date of Patent: October 9, 2007Assignee: Intel CorporationInventors: Ali Keshavarzi, Fabrice Paillet, Muhammad M. Khellah, Dinesh Somasekhar, Yibin Ye, Stephen H. Tang, Mohsen Alavi, Vivek K. De
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Publication number: 20070076463Abstract: According to embodiments of the present invention, a one-time programmable (OTP) cell includes an access transistor coupled to an antifuse transistor. In on embodiment, access transistor has a gate oxide thickness that is greater than the gate oxide thickness of the antifuse transistor so that if the antifuse transistor is programmed, the voltage felt across the gate/drain junction of the access transistor is insufficient to cause the gate oxide of the access transistor to break down. The dual gate oxide OTP cell may be used in an array in which only one OTP cell is programmed at a time. The dual gate oxide OTP cell also may be used in an array in which several OTP cells are programmed simultaneously.Type: ApplicationFiled: September 30, 2005Publication date: April 5, 2007Inventors: Ali Keshavarzi, Fabrice Paillet, Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Stephen Tang, Mohsen Alavi, Vivek De
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Patent number: 7167397Abstract: A method of programming a memory array is provided, including accessing a plurality of word lines of the memory array by providing a plurality of voltage steps sequentially after one another to the respective word lines, and accessing a plurality of bit lines of the memory array each time that a respective word line is accessed, to program a plurality of devices corresponding to individual word and bit lines that are simultaneously accessed, each device being programmed by breaking a dielectric layer of the device, accessing of the bit lines being sequenced such that only a single one of the devices is programmed at a time.Type: GrantFiled: June 21, 2005Date of Patent: January 23, 2007Assignee: Intel CorporationInventors: Fabrice Paillet, Ali Keshavarzi, Muhammad M. Khellah, Dinesh Somasekhar, Yibin Ye, Stephen H. Tang, Mohsen Alavi, Vivek K. De, Tanay Karnik
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Publication number: 20060285393Abstract: A method of programming a memory array is provided, including accessing a plurality of word lines of the memory array by providing a plurality of voltage steps sequentially after one another to the respective word lines, and accessing a plurality of bit lines of the memory array each time that a respective word line is accessed, to program a plurality of devices corresponding to individual word and bit lines that are simultaneously accessed, each device being programmed by breaking a dielectric layer of the device, accessing of the bit lines being sequenced such that only a single one of the devices is programmed at a time.Type: ApplicationFiled: June 21, 2005Publication date: December 21, 2006Inventors: Fabrice Paillet, Ali Keshavarzi, Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Stephen Tang, Mohsen Alavi, Vivek De, Tanay Karnik
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Patent number: 7110278Abstract: Crosspoint memory arrays utilizing one time programmable antifuse cells are disclosed.Type: GrantFiled: September 29, 2004Date of Patent: September 19, 2006Assignee: Intel CorporationInventors: Ali Keshavarzi, Fabrice Paillet, Muhammad M. Khellah, Dinesh Somasekhar, Yibin Ye, Stephen H. Tang, Mohsen Alavi, Vivek K. De
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Patent number: 7102358Abstract: A transistor may have degraded characteristics because of an overvoltage condition. The degraded characteristics may be sensed to determine that the transistor has previously been subjected to an overvoltage condition.Type: GrantFiled: June 29, 2004Date of Patent: September 5, 2006Assignee: Intel CorporationInventors: Ali Keshavarzi, Fabrice Paillet, Muhammad M Khellah, Dinesh Somasekhar, Yibin Ye, Stephen H Tang, Mohsen Alavi, Vivek K De
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Patent number: 7102951Abstract: Different embodiments of a one-time-programmable antifuse cell included. In one embodiment, a circuit is provided that includes an antifuse element, a high voltage device, and a sense circuit. The antifuse element has a voltage supply terminal to be at a sense voltage during sensing/reading and a higher programming voltage during programming. The sense circuit is configured to enable programming the antifuse element during programming and to sense the state of the antifuse element during sensing. The high voltage device is coupled between the antifuse element and the sense circuit to couple the antifuse element to the sense circuit during programming and sensing and to protectively shield the sense circuit from the higher programming voltage during programming.Type: GrantFiled: November 1, 2004Date of Patent: September 5, 2006Assignee: Intel CorporationInventors: Fabrice Paillet, Ali Keshavarzi, Muhammad M. Khellah, Dinesh Somasekhar, Yibin Ye, Stephen H. Tang, Mohsen Alavi, Vivek K. De
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Publication number: 20060139995Abstract: A one time programmable memory includes isolated gate transistors that may be programmed by subjecting the isolated gate transistors to voltage conditions that degrade characteristics of the isolated gate transistors. The degraded characteristics may be sensed to read the memory.Type: ApplicationFiled: December 28, 2004Publication date: June 29, 2006Inventors: Ali Keshavarzi, Fabrice Paillet, Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Stephen Tang, Mohsen Alavi, Vivek De
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Publication number: 20060092742Abstract: Different embodiments of a one-time-programmable antifuse cell are provided in this disclosure. In one embodiment, a circuit is provided that includes an antifuse element, a high voltage device, and a sense circuit. The antifuse element has a voltage supply terminal to be at a sense voltage during sensing/reading and a higher programming voltage during programming. The sense circuit is configured to enable programming the antifuse element during programming and to sense the state of the antifuse element during sensing. The high voltage device is coupled between the antifuse element and the sense circuit to couple the antifuse element to the sense circuit during programming and sensing and to protectively shield the sense circuit from the higher programming voltage during programming.Type: ApplicationFiled: November 1, 2004Publication date: May 4, 2006Inventors: Fabrice Paillet, Ali Keshavarzi, Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Stephen Tang, Mohsen Alavi, Vivek De
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Publication number: 20060067152Abstract: Crosspoint memory arrays utilizing one time programmable antifuse cells are disclosed.Type: ApplicationFiled: September 29, 2004Publication date: March 30, 2006Inventors: Ali Keshavarzi, Fabrice Paillet, Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Stephen Tang, Mohsen Alavi, Vivek De
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Publication number: 20050285616Abstract: A transistor may have degraded characteristics because of an overvoltage condition. The degraded characteristics may be sensed to determine that the transistor has previously been subjected to an overvoltage condition.Type: ApplicationFiled: June 29, 2004Publication date: December 29, 2005Inventors: Ali Keshavarzi, Fabrice Paillet, Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Stephen Tang, Mohsen Alavi, Vivek De
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Patent number: 6903598Abstract: A fuse-based cell. The fuse-based cell includes a fuse with a programming device electrically coupled to the fuse to program the fuse. A sensing device is electrically coupled to the fuse to sense a programming state of the fuse. A clamping device is electrically coupled to the sensing device to control voltages across the sensing device during programming. A pass device is electrically coupled to the sensing device to control voltages across the sensing device during sensing.Type: GrantFiled: May 24, 2002Date of Patent: June 7, 2005Assignee: Intel CorporationInventors: Martin Spence Denham, Mohsen Alavi, Kaizad Rumy Mistry, Patrick John Ott, Rachael Jade Parker, Paul Gregory Slankard, Wenliang Chen
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Publication number: 20030218492Abstract: A fuse-based cell. The fuse-based cell includes a fuse with a programming device electrically coupled to the fuse to program the fuse. A sensing device is electrically coupled to the fuse to sense a programming state of the fuse. A clamping device is electrically coupled to the sensing device to control voltages across the sensing device during programming. A pass device is electrically coupled to the sensing device to control voltages across the sensing device during sensing.Type: ApplicationFiled: May 24, 2002Publication date: November 27, 2003Applicant: Intel CorporationInventors: Martin Spence Denham, Mohsen Alavi, Kaizad Rumy Mistry, Patrick John Ott, Rachael Jade Parker, Paul Gregory Slankard, Wenliang Chen
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Patent number: 6624032Abstract: A dual gate transistor device and method for fabricating the same. First, a doped substrate is prepared with a patterned oxide layer on the doped substrate defining a channel. Next, a silicon layer is deposited to form the channel, with a gate oxide layer then grown adjacent the channel. Subsequently, a plurality of gate electrodes are formed next to the gate oxide layer and a drain is formed on the channel. After the drain is formed, an ILD layer is deposited. This ILD layer is etched to form a source region contact, a drain region contact, a first gate electrode contact, and a second gate electrode contact.Type: GrantFiled: March 20, 2002Date of Patent: September 23, 2003Assignee: Intel CorporationInventors: Mohsen Alavi, Ebrahim Andideh, Scott Thompson, Mark T. Bohr
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Publication number: 20020098657Abstract: A dual gate transistor device and method for fabricating the same. First, a doped substrate is prepared with a patterned oxide layer on the doped substrate defining a channel. Next, a silicon layer is deposited to form the channel, with a gate oxide layer then grown adjacent the channel. Subsequently, a plurality of gate electrodes are formed next to the gate oxide layer and a drain is formed on the channel. After the drain is formed, an ILD layer is deposited. This ILD layer is etched to form a source region contact, a drain region contact, a first gate electrode contact, and a second gate electrode contact.Type: ApplicationFiled: March 20, 2002Publication date: July 25, 2002Inventors: Mohsen Alavi, Ebrahim Andideh, Scott Thompson, Mark T. Bohr
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Patent number: 6392271Abstract: A dual gate transistor device and method for fabricating the same. First, a doped substrate is prepared with a patterned oxide layer on the doped substrate defining a channel. Next, a silicon layer is deposited to form the channel, with a gate oxide layer then grown adjacent the channel. Subsequently, a plurality of gate electrodes are formed next to the gate oxide layer and a drain is formed on the channel. After the drain is formed, an ILD layer sited. This ILD layer is etched to form a source region contact, a drain region contact, a first gate electrode contact, and a second gate electrode contact.Type: GrantFiled: June 28, 1999Date of Patent: May 21, 2002Assignee: Intel CorporationInventors: Mohsen Alavi, Ebrahim Andideh, Scott Thompson, Mark T. Bohr
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Publication number: 20020034853Abstract: A dual gate transistor device and method for fabricating the same. First, a doped substrate is prepared with a patterned oxide layer on the doped substrate defining a channel. Next, a silicon layer is deposited to form the channel, with a gate oxide layer then grown adjacent the channel. Subsequently, a plurality of gate electrodes are formed next to the gate oxide layer and a drain is formed on the channel. After the drain is formed, an ILD layer is deposited. This ILD layer is etched to form a source region, a drain region, a first gate electrode, and a second gate electrode.Type: ApplicationFiled: June 28, 1999Publication date: March 21, 2002Inventors: MOHSEN ALAVI, EBRAHIM ANDIDEH, SCOTT THOMPSON, MARK T. BOHR
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Patent number: 6337507Abstract: A fusible link device disposed on a semiconductor substrate for providing discretionary changes in resistance. The fusible link device of the invention includes a polysilicon layer having a first resistance. A silicide layer formed on the polysilicon layer has a second, lower resistance and includes a fuse region having a first notched region narrower than the center of the fuse region, a first contact region electrically coupled to one end of the fuse region and a second contact region electrically coupled to an opposite end of the fuse region. The silicide layer agglomerates to form an electrical discontinuity in the fuse region (usually in the notched region) in response to a current greater than or equal to a predetermined programming current flowing between the contact regions, such that the resistance of the fusible link device can be selectively increased.Type: GrantFiled: December 18, 1996Date of Patent: January 8, 2002Assignee: Intel CorporationInventors: Mark T. Bohr, Mohsen Alavi, Min-Chun Tsai
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Patent number: 6258700Abstract: A fusible link device disposed on a semiconductor substrate for providing discretionary electrical connections. The fusible link device of the invention includes a silicide layer and a polysilicon layer formed on the silicide layer and has a first un-programmed resistance. The silicide layer agglomerates to form an electrical discontinuity in response to a predetermined programming potential being applied across the suicide layer, such that the resistance of the fusible link device can be selectively increased to a second programmed resistance.Type: GrantFiled: May 18, 1999Date of Patent: July 10, 2001Assignee: Intel CorporationInventors: Mark T. Bohr, Mohsen Alavi
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Patent number: 6096610Abstract: A method and an apparatus for forming a transistor suitable for a high voltage circuit. In one embodiment, the transistor is formed without adding any steps to an existing state-of-the-art CMOS process. A well is implanted into a portion of a substrate such that the well has a higher doping concentration than the substrate. A first diffusion region is then implanted into the substrate such that at least a portion of the first diffusion is disposed within the well. In addition, a second diffusion is implanted into the substrate separated from the well such that the second diffusion region is disposed entirely outside the well. A channel region is disposed between the first and second regions and gate is disposed over the channel region to form the high voltage transistor. Since the second diffusion region is disposed entirely outside the well in the lower doped substrate, a higher junction breakdown voltage is realized.Type: GrantFiled: January 8, 1997Date of Patent: August 1, 2000Assignee: Intel CorporationInventors: Mohsen Alavi, Tahir Ghani