Abstract: Systems, methods, and computer programs are disclosed for reducing power consumption for static image display refresh in a dynamic random access memory (DRAM) memory system. One such method comprises: prefetching static image frame content from a DRAM memory device into a system cache; during a static display refresh operation, a display processor reads the static image frame content from the system cache while the DRAM memory device is in a power-saving, self-refresh state; and the display processor feeding the static image frame content to a mobile display.

Abstract: Devices and methods for monitoring one or more central processing units in real time are disclosed. The method may include monitoring state data associated with the one or more CPUs in real-time, filtering the state data, and at least partially based on filtered state data, selectively altering one or more system settings. A device may include means for monitoring state data associated with the one or more CPUs in real-time, means for filtering the state data, and means for selectively altering one or more system settings at least partially based on filtered state data. A device may also include a sub-sampling circuit configured to receive a hardware core signal from the central processing unit and output a central processing unit state indication, and an infinite impulse response filter connected to the sub-sampling circuit and configured to receive the central processing unit state indication from the sub-sampling circuit.

Abstract: Devices, systems, methods, and computer-readable mediums for arbitrating bus transactions on a communications bus based on health information are disclosed. Health information of master devices can be used to adjust priorities of bus transactions from master devices to meet quality of service requirements of the master devices. In one embodiment, a bus interconnect is provided and configured to communicate bus transactions from any of a plurality of master devices to slave device(s) coupled the bus interconnect. The bus interconnect is further configured to map health information for each of the plurality of master devices into virtual priority space. The bus interconnect is further configured to translate the virtual priority space into a physical priority level for each of the plurality of master devices. The bus interconnect is further configured to arbitrate bus transactions for the plurality of master devices based on physical priority level for the plurality of master devices.

Abstract: A method and system for message multicasting which provides a programmable persistent header in a message to allow one message to be read by multiple target consumers and to ensure that the message passing mechanism does not delete the message until all target consumers have received it. The persistent header may have information about all target consumers and their priority to consume the message. A message parser may obtain from the persistent header identities of target consumers and the order in which they consume the message and allow target consumers to consume the message following the order. The message parser may have a counter which counts the number of consumers that have consumed the message, and keep the message in the queue until all target consumers have consumed the message.

Abstract: An embodiment of the present invention includes a multi-core processor that processes video data. The control core controls a first processing core to process a first set of data blocks of an image frame according to a stairstep pattern. The control core detects, while the first processing core is processing the first set, that a triggering data block has been processed in the first set. The control core controls, while the first processing core is processing the first set, a second processing core to process a second set of data blocks using information from the triggering data block. By processing data blocks in the stairstep pattern, cache hit rate is improved, resulting in improved video decoder performance.

Abstract: A system including an image data source and a transfer function module. The image data source is configured to provide image data. The transfer function module is configured to generate a transfer function to process the image data, define a first region of the transfer function, wherein a curvature of the transfer function in the first region is less than or equal to a threshold, define a second region of the transfer function, wherein a curvature of the transfer function in the second region is greater than the threshold, allocate a first number of sample inputs to the first region, allocate a second number of the sample inputs to the second region, wherein the second number is greater than the first number, map the sample inputs to sample outputs using the transfer function, and populate entries of a lookup table with the sample outputs.

Abstract: Devices, systems, methods, and other embodiments associated with clipping instructions are described. In one embodiment, an apparatus includes a receive logic to receive the clipping instruction. The clipping instruction includes a pixel value to be clipped and a clipping boundary. The apparatus also includes an execution logic to execute the clipping instruction in one clock cycle. The clipping instruction clips pixels by comparing a magnitude of the pixel value identified in the clipping instruction to a magnitude of the clipping boundary identified in the clipping instruction. When the magnitude of the pixel value exceeds the magnitude of the clipping boundary, the pixel is selectively clipped to a result value.

Abstract: In an embodiment, an apparatus includes a cryptographic processor within a wireless device. The cryptographic processor includes at least one cryptographic unit. The cryptographic processor also includes a nonvolatile memory to store one or more microcode instructions, wherein at least one of the one or more microcode instructions is related to a sensitive operation. The cryptographic processor also includes a controller to control execution of the one or more microcode instructions by the at least one cryptographic unit, wherein the controller is to preclude execution of the sensitive operation if the apparatus is within an untrusted state.

Abstract: In one or more embodiments, an apparatus comprises an alignment module implemented in hardware to identify requested data that is not aligned on a natural alignment boundary of a memory and load at least two sets of neighboring data such that each said set includes at least a portion of the requested data. The alignment module is further configured to extract the requested data from the at least two sets of neighboring data and output the extracted data to a processor.

Abstract: Transfer functions are often used for image processing. Look-up tables can be used to implement transfer functions in a processor-efficient manner. In one embodiment, the invention is an apparatus that includes a look-up table (LUT) storing sample outputs from an output range of a transfer function, the sample outputs corresponding to sample inputs from an input range of the transfer function, the sample inputs being distributed so that more sample inputs are associated with a first region of the transfer function than a second region of the transfer function; and an address module to calculate an index into the LUT based on image data. In one embodiment, the apparatus uses the LUT to process the image data.

Abstract: A method and system for message multicasting which provides a programmable persistent header in a message to allow one message to be read by multiple target consumers and to ensure that the message passing mechanism does not delete the message until all target consumers have received it. The persistent header may have information about all target consumers and their priority to consume the message. A message parser may obtain from the persistent header identities of target consumers and the order in which they consume the message and allow target consumers to consume the message following the order. The message parser may have a counter which counts the number of consumers that have consumed the message, and keep the message in the queue until all target consumers have consumed the message.

Abstract: An apparatus includes an input module and a color synthesis module. The input module is configured to receive mosaic image data representing an image. The mosaic image data includes radial distortion. The color synthesis module, implemented in digital electronic circuitry, includes a radial distortion correction module and a synthesis module. The radial distortion correction module is configured to receive the mosaic image data and generate correction data to correct the radial distortion in the mosaic image data. The synthesis module is configured to receive the mosaic image data and the correction data, wherein the mosaic image data includes a plurality of input pixel values and respective input pixel locations prior to being corrected, and generate demosaiced image data using the mosaic image data and the correction data.

Abstract: A server including a partitioning module and a transmit module. The partitioning module is configured to partition data at an application layer of the server, where the data is to be transmitted from the server to a handheld device concurrently via i) a first wireless link and ii) a second wireless link, and where the partitioning is performed in response to a rate of flow of data via i) the first wireless link or ii) the second wireless link. The partitioning module is configured to partition data, received from the application layer, at a session layer of the server into i) a first component and ii) a second component. The transmit module is configured to concurrently transmit from the server to the handheld device i) the first component via the first wireless link and ii) the second component via the second wireless link.

Abstract: Devices, systems, methods, and other embodiments associated with clipping instructions are described. In one embodiment, a method includes receiving a clipping instruction for clipping filtered values in a video image de-blocking operation. The clipping instruction references a video data value and a clipping value. The method includes decoding the clipping instruction. The method also includes retrieving the video data value and the clipping value. A video data magnitude of the video data value is determined. The method determines a clipping magnitude of the clipping value. A determination is made as to whether the video data magnitude exceeds the clipping magnitude. If the video data magnitude exceeds the clipping magnitude, the video data value is selectively clipped.

Abstract: Devices, systems, methods, and other embodiments associated with block type selection are described. In one embodiment, a method calculates for each block from a set of M×N blocks that form a macroblock of image data, a first set of data. Adjacent blocks of the set of M×N blocks are combined into composite blocks. Data of the first set of data is selectively forwarded to composite blocks. For each composited block, a second set of data is calculated based, at least in part, on the forwarded data. A participation block is selected from one of the set of M×N blocks and the set of composite blocks based, at least in part, on the first set of data and the second set of data. The macroblock is compressed based on the participation block.

Abstract: Memory access instructions, such as load and store instructions, are processed in a processor-based system. Processor hardware pipeline configurations enable efficient performance of memory access instructions, such as a pipeline configuration that enables, for a memory access operation request by a register-operand based virtual machine, computation of the memory location corresponding to a virtual-machine register by extracting a bit-field from the virtual-machine instruction and accessing (load or store) the computed memory location that represents a virtual register of the virtual-machine, in a single pass through the pipeline. Thus this processor hardware pipeline configuration enables a virtual machine register read/write operation to be performed by a single hardware processor instruction through a single pass in the processor hardware pipeline, for a register-operand based virtual machine.

Abstract: In one embodiment the present invention includes a method and apparatus for enabling a main core and one or more co-processors to operate in a de-coupled mode, thereby facilitating the execution of two or more instruction threads in parallel. A co-processor, according to an embodiment of the invention, has a coupling manager including a loop buffer for storing instructions which can be independently fetched and executed by the co-processor when operating in de-coupled mode. In addition, the coupling manager includes a loop descriptor and a counter/condition descriptor. The loop descriptor and condition descriptor work in conjunction with one another to determine what, if any, action should be taken when a co-processor is in a particular processing state, for example, as indicated by a counter keeping track of loop processing.

Abstract: Systems and methods are provided for calculating a motion vector for a macroblock between a reference frame and a current frame. The system includes a main processor. The system further includes a programmable video accelerator configured to receive a linked list of variable length descriptor inputs at the direction of the main processor. The descriptor inputs include the macroblock for which the motion vector is to be calculated. The video accelerator is further configured to calculate a motion vector identifying motion of the identified macroblock from the reference frame to the current frame.

Abstract: In accordance with the teachings described herein, systems and methods are provided for identifying a block of pixel data in a reference frame. The system may include a data fetch, a shift register, and one or more processing blocks. The data fetch may receive a best fit integer block, where the best fit integer block is identified by comparing the current block of pixel data to a search area within a reference block of pixel data. The shift register may be configured to load pixel data to be used for performing a fractional pixel expansion for one quadrant corresponding to each integer pixel in a block of pixel data, the block of pixel data including the best fit integer block plus one additional row of integer pixels and one additional column of integer pixels, wherein a combination of all of the one quadrant fractional expansions provides a plurality of fractional blocks for the best fit integer block.

Abstract: A network is disclosed. The network includes a server computer, a first wireless communications link communicatively coupled to the server computer, a second wireless communications link communicatively coupled to the server computer, and a handheld device communicatively coupled to the first and second wireless communications links. The handheld device concurrently receives an object from the server computer via the first and second wireless communications links.