Abstract: In accordance with the teachings described herein, systems and methods are provided for scanning a search area of reference pixel data to identify a reference macroblock of pixels with a closest pixel fit to a current macroblock of pixels. An example system may include a local memory array (e.g., a shift register), a processing block and a scan sequencer. The local memory array may include a plurality of rows and columns, with N extra rows or columns in addition to a number of rows or columns necessary to store N reference macroblocks of pixels The processing block may be used to compare reference macroblocks of pixels with the current macroblock of pixels to identify the reference macroblock of pixels with the closest pixel fit to the current macroblock of pixels. The scan sequencer may be used to load reference pixel data into the local memory array and present reference macroblocks of pixels from the local memory array to the processing block according to a scan pattern.

Abstract: Devices, systems, methods, and computer-readable mediums for arbitrating bus transactions on a communications bus based on health information are disclosed. Health information of master devices can be used to adjust priorities of bus transactions from master devices to meet quality of service requirements of the master devices. In one embodiment, a bus interconnect is provided and configured to communicate bus transactions from any of a plurality of master devices to slave device(s) coupled the bus interconnect. The bus interconnect is further configured to map health information for each of the plurality of master devices into virtual priority space. The bus interconnect is further configured to translate the virtual priority space into a physical priority level for each of the plurality of master devices. The bus interconnect is further configured to arbitrate bus transactions for the plurality of master devices based on physical priority level for the plurality of master devices.

Abstract: In one or more embodiments, a method, computer-readable media, system and or modules are capable of generating an address for a multimedia data block included in a stream of multimedia data. The address can be maintained in one or more local registers. The one or more local registers can be linked to one or more processor registers associated with a processor to synchronize communication of the stream of multimedia data with the processor.

Abstract: During operation of a VLIW processor, a very long instruction word is fetched. A portion of the very long instruction word that includes a pointer to an instruction is identified, and the instruction pointed to by the pointer is retrieved from a location of an instruction window. The retrieved instruction is input into a functional unit for execution.

Abstract: Apparatus having corresponding methods and computer programs comprise an input module to receive image data representing an image, wherein the image data includes radial distortion; and a zoom module to scale the image based on the image data and a scaling factor, wherein the zoom module comprises a radial distortion correction module to correct the radial distortion in the image data while the zoom module scales the image.

Abstract: Methods and apparatus for calculating Single-Instruction-Multiple-Data (SIMD) complex arithmetic. A coprocessor instruction has a format identifying a multiply and subtract instruction to generate real components for complex multiplication of first operand complex data and corresponding second operand complex data, a cross multiply and add instruction to generate imaginary components for complex multiplication of the first operand complex data and the corresponding second operand complex data, an add-subtract instruction to add real components of the first operand to imaginary components of the second operand and to subtract real components of the second operand from imaginary components of the first operand, and a subtract-add instruction to subtract the imaginary components of the second operand from the real components of the first operand and to add the real components of the second operand to the imaginary components of the first operand.

Abstract: In an embodiment, an apparatus includes a trusted cryptographic processor that includes at least one functional unit. The trusted cryptographic processor also includes a controller to receive a primitive instruction that identifies which of the at least one functional unit is to perform an operation, wherein the controller is to reduce power to the at least one functional unit that is not identified by the primitive instruction. The apparatus includes a trusted power management unit to supply the power based on control from the controller, wherein the control is independent of a processor that is not in a trusted state.

Abstract: In an embodiment, an apparatus includes one or more cryptographic units. The apparatus also includes a memory to store one or more data encryption keys and an associated header for the one or more data encryption keys. The associated header defines which of the one or more cryptographic units are to use the data encryption key.

Abstract: In an embodiment, an apparatus includes a trusted cryptographic processor that includes at least one functional unit. The trusted cryptographic processor also includes a controller to receive a primitive instruction that identifies which of the at least one functional unit is to perform an operation, wherein the controller is to reduce power to the at least one functional unit that is not identified by the primitive instruction. The apparatus includes a trusted power management unit to supply the power based on control from the controller, wherein the control is independent of a processor that is not in a trusted state.

Abstract: In an embodiment, an apparatus includes a cryptographic processor within a wireless device. The cryptographic processor includes at least one cryptographic unit. The cryptographic processor also includes a nonvolatile memory to store one or more microcode instructions, wherein at least one of the one or more microcode instructions is related to a sensitive operation. The cryptographic processor also includes a controller to control execution of the one or more microcode instructions by the at least one cryptographic unit, wherein the controller is to preclude execution of the sensitive operation if the apparatus is within an untrusted state.

Abstract: Trusted code may be patched in a manner that resists tampering from non-trusted sources. In some embodiments, the patches may be moved into a patch cache in a trusted processing module for execution.

Abstract: Methods and apparatus for calculating Single-Instruction-Multiple-Data (SIMD) complex arithmetic. A coprocessor instruction has a format identifying a multiply and subtract instruction to generate real components for complex multiplication of first operand complex data and corresponding second operand complex data, a cross multiply and add instruction to generate imaginary components for complex multiplication of the first operand complex data and the corresponding second operand complex data, an add-subtract instruction to add real components of the first operand to imaginary components of the second operand and to subtract real components of the second operand from imaginary components of the first operand, and a subtract-add instruction to subtract the real components of the second operand from the imaginary components of the first operand and to add the real components of the first operand to the imaginary components of the second operand.

Abstract: During debug operations in one embodiment of a trusted subsystem, passwords may be used to enable and disable access to selected areas, and to make access by different entities mutually exclusive. In another embodiment, programmable units may be used to define what the selected areas of access are for debug operations.

Abstract: A system, apparatus, method, and article to reduce display bandwidth are described. The apparatus may include a display controller to identify an opaque region in windows defining an output image. The display controller determines an overlay order for any overlapping portions of the windows. A higher order window overlays a lower order window. The display controller fetches data defining the opaque region only from an uppermost overlay window prior to displaying the output image.

Abstract: A dynamic cache-locking algorithm may determine the most frequently used function(s) and the number of cache lines that should be locked into the instruction cache embedded into a processor. By evaluating the dynamic cache-locking algorithm, a determination may be made to lock an optimal amount of functions that correspond to a given, limited amount of instruction cache.

Abstract: A technique to manage multiple-mapped memory and to selectively execute at least a portion of a process from either an unprotected function or a protected function. The process contains memory that is multiple-mapped to both an unprotected memory region and to a protected memory region that stores a protected function. A trust co-processor determines whether the process is a trusted process or an untrusted process. If trusted, the multiple-mapped memory is mapped to the protected memory region; and a transfer agent operates to control the process and to call the protected function using parameters provided to the transfer agent from the process. In one embodiment, the transfer agent resides in nonvolatile memory, and is transferred to internal SRAM to control execution of a trusted process.

Abstract: A method and apparatus to perform memory management are described.

Abstract: A dynamic cache-locking algorithm may determine the most frequently used function(s) and the number of cache lines that should be locked into the instruction cache embedded into a processor. By evaluating the dynamic cache-locking algorithm, a determination may be made to lock an optimal amount of functions that correspond to a given, limited amount of instruction cache.

Abstract: A cellular communication system with enhanced Quality-of-Service (QoS) during the hand-off process is disclosed. The system includes a plurality of cells, each including a corresponding base station. Based on the history of a mobile user's positions, the base station of the cell in which the user is located predicts the user's future position. If the future position is in an area covered by another base station (i.e., the target base station), the base station initiates QoS negotiations with the target base station. The target base station allocates resources according to the negotiated QoS if the mobile user enters the area covered by the target base station as predicted.

Abstract: A translation look-aside buffer (TLB) has lockable entries. A number of entries to lock may be determined by counting unique page access instances during an active period of a process, determining a value of a page usage metric for the process, and comparing the value of the page usage metric to values of page usage metrics for other processes. The page usage metric may consider many different factors, including the amount of time a process is active, a frequency of invocation of the process, and a priority level of a process.