Abstract: An integrated circuit includes a metal-oxide semiconductor field-effect transistor (MOSFET) formed in and over a semiconductor substrate. The MOSFET has a gate structure that includes a gate dielectric layer formed the substrate and a gate electrode located over the gate dielectric layer. A pre-metal dielectric layer is over the gate electrode layer, and an electrical contact through the pre-metal dielectric layer connects to the gate electrode. The polysilicon layer has a mean grain size of 50 nanometers (nm) or less.

Abstract: Described examples include an integrated circuit having a substrate. The integrated circuit also has at least one dummy cell on the substrate, the dummy cell having at least a first component having an edge in a first layer of components on the substrate and at least a second component in a second layer of components, the second layer of components on the first layer of components and the substrate, wherein no part of the second component is proximate to the edge of the first component. The integrated circuit also has an insulating layer on the first layer of components and the second layer of components, the insulating layer having a first surface opposite to a second surface of the insulating layer on the first layer of components and the second layer of components, wherein the first surface is planarized and a patterned conductor layer on the first surface.

Abstract: A system and method for growing fine grain polysilicon. In one example, the method of forming an integrated circuit includes forming a dielectric layer over a semiconductor substrate, and forming a polysilicon layer over the dielectric layer. The polysilicon layer is formed by a chemical vapor deposition process that includes providing a gas flow including disilane and hydrogen gas over the semiconductor substrate.

Abstract: A system and method for growing fine grain polysilicon. In one example, the method of forming an integrated circuit includes forming a dielectric layer over a semiconductor substrate, and forming a polysilicon layer over the dielectric layer. The polysilicon layer is formed by a chemical vapor deposition process that includes providing a gas flow including disilane and hydrogen gas over the semiconductor substrate.

Abstract: A method of fabricating a semiconductor device includes aligning an alignment structure of a wafer to a direction of a magnetic field created by an external electromagnet and depositing a magnetic layer (e.g., NiFe) over the wafer in the presence of the magnetic field and while applying the magnetic field and maintaining a temperature of the wafer below 150° C. An insulation layer (e.g., AlN) is deposited on the first magnetic layer. The alignment structure of the wafer is again aligned to the direction of the magnetic field and a second magnetic layer is deposited on the insulation layer, in the presence of the magnetic field and while maintaining the temperature of the wafer below 150° C.

Abstract: A method of magnetic forming an integrated fluxgate sensor includes providing a patterned magnetic core on a first nonmagnetic metal or metal alloy layer on a dielectric layer over a first metal layer that is on or in an interlevel dielectric layer (ILD) which is on a substrate. A second nonmagnetic metal or metal alloy layer is deposited including over and on sidewalls of the magnetic core. The second nonmagnetic metal or metal alloy layer is patterned, where after patterning the second nonmagnetic metal or metal alloy layer together with the first nonmagnetic metal or metal alloy layer encapsulates the magnetic core to form an encapsulated magnetic core. After patterning, the encapsulated magnetic core is magnetic field annealed using an applied magnetic field having a magnetic field strength of at least 0.1 T at a temperature of at least 150° C.

Abstract: A method comprises forming an etch stop layer, a first titanium layer, a magnetic core, a second titanium layer, and patterning the first and second titanium layers. The etch stop layer is formed above a substrate. The first titanium layer is formed on the etch stop layer. The magnetic core is formed on the first titanium layer. The second titanium layer has a first portion encapsulating the magnetic core with the first titanium layer, and a second portion interfacing with the first titanium layer beyond the magnetic core. The patterning of the first and second titanium layers includes forming a mask over a magnetic core region and etching the first and second titanium layers exposed by the mask using a titanium etchant and a titanium oxide etchant.

Abstract: A method comprises forming an etch stop layer, a first titanium layer, a magnetic core, a second titanium layer, and patterning the first and second titanium layers. The etch stop layer is formed above a substrate. The first titanium layer is formed on the etch stop layer. The magnetic core is formed on the first titanium layer. The second titanium layer has a first portion encapsulating the magnetic core with the first titanium layer, and a second portion interfacing with the first titanium layer beyond the magnetic core. The patterning of the first and second titanium layers includes forming a mask over a magnetic core region and etching the first and second titanium layers exposed by the mask using a titanium etchant and a titanium oxide etchant.

Abstract: A method of fabricating a semiconductor device includes aligning an alignment structure of a wafer to a direction of a magnetic field created by an external electromagnet and depositing a magnetic layer (e.g., NiFe) over the wafer in the presence of the magnetic field and while applying the magnetic field and maintaining a temperature of the wafer below 150° C. An insulation layer (e.g., AlN) is deposited on the first magnetic layer. The alignment structure of the wafer is again aligned to the direction of the magnetic field and a second magnetic layer is deposited on the insulation layer, in the presence of the magnetic field and while maintaining the temperature of the wafer below 150° C.

Abstract: A method comprises forming an etch stop layer, a first titanium layer, a magnetic core, a second titanium layer, and patterning the first and second titanium layers. The etch stop layer is formed above a substrate. The first titanium layer is formed on the etch stop layer. The magnetic core is formed on the first titanium layer. The second titanium layer has a first portion encapsulating the magnetic core with the first titanium layer, and a second portion interfacing with the first titanium layer beyond the magnetic core. The patterning of the first and second titanium layers includes forming a mask over a magnetic core region and etching the first and second titanium layers exposed by the mask using a titanium etchant and a titanium oxide etchant.

Abstract: A method comprises forming an etch stop layer, a first titanium layer, a magnetic core, a second titanium layer, and patterning the first and second titanium layers. The etch stop layer is formed above a substrate. The first titanium layer is formed on the etch stop layer. The magnetic core is formed on the first titanium layer. The second titanium layer has a first portion encapsulating the magnetic core with the first titanium layer, and a second portion interfacing with the first titanium layer beyond the magnetic core. The patterning of the first and second titanium layers includes forming a mask over a magnetic core region and etching the first and second titanium layers exposed by the mask using a titanium etchant and a titanium oxide etchant.

Abstract: A method of magnetic forming an integrated fluxgate sensor includes providing a patterned magnetic core on a first nonmagnetic metal or metal alloy layer on a dielectric layer over a first metal layer that is on or in an interlevel dielectric layer (ILD) which is on a substrate. A second nonmagnetic metal or metal alloy layer is deposited including over and on sidewalls of the magnetic core. The second nonmagnetic metal or metal alloy layer is patterned, where after patterning the second nonmagnetic metal or metal alloy layer together with the first nonmagnetic metal or metal alloy layer encapsulates the magnetic core to form an encapsulated magnetic core. After patterning, the encapsulated magnetic core is magnetic field annealed using an applied magnetic field having a magnetic field strength of at least 0.1 T at a temperature of at least 150° C.

Abstract: A method for forming a through silicon via (TSV) in a substrate comprising: depositing a seed layer in a TSV hole; and annealing the seed layer.

Abstract: Methods (102) are presented for protecting copper structures (26) from corrosion in the fabrication of semiconductor devices (2), wherein a thin semiconductor or copper-semiconductor alloy corrosion protection layer (30) is formed on an exposed surface (26a) of a copper structure (26) prior to performance of metrology operations (206), so as to inhibit corrosion of the copper structure (26). All or a portion of the corrosion protection layer (30) is then removed (214) in forming an opening in an overlying dielectric (44) in a subsequent interconnect layer.

Abstract: A post chemical-mechanical polishing cleaning method, comprising contacting a die with a first chemistry that removes at least some organic compounds and ions from a surface of the die. After contacting the die with the first chemistry, the method further comprises contacting the die with a second chemistry that removes at least some copper abutting the die surface. The method further comprises rinsing and drying the die.

Abstract: A method (100) of fabricating an electronic device (200) formed on a semiconductor wafer. The method forms a layer (215) of a first material in a fixed position relative to the wafer. The first material has a dielectric constant less than 3.6. The method also forms a photoresist layer in (216) a fixed position relative to the layer of the first material. The method also forms at least one void (220) through the layer of the first material in response to the photoresist layer. Further, the method subjects (106) the semiconductor wafer to a plasma which incorporates a gas which includes hydrogen so as to remove the photoresist layer.

Abstract: Methods (102) are presented for protecting copper structures (26) from corrosion in the fabrication of semiconductor devices (2), wherein a thin semiconductor or copper-semiconductor alloy corrosion protection layer (30) is formed on an exposed surface (26a) of a copper structure (26) prior to performance of metrology operations (206), so as to inhibit corrosion of the copper structure (26). All or a portion of the corrosion protection layer (30) is then removed (214) in forming an opening in an overlying dielectric (44) in a subsequent interconnect layer.

Abstract: A post chemical-mechanical polishing cleaning method, comprising contacting a die with a first chemistry that removes at least some organic compounds and ions from a surface of the die. After contacting the die with the first chemistry, the method further comprises contacting the die with a second chemistry that removes at least some copper abutting the die surface. The method further comprises rinsing and drying the die.

Abstract: The invention describes a method for the selective dry etching of tantalum and tantalum nitride films. Tantalum nitride layers (30) are often used in semiconductor manufacturing. The semiconductor substrate is exposed to a reducing plasma chemistry which passivates any exposed copper (40). The tantalum or tantalum nitride films are selectively removed using an oxidizing plasma chemistry.

Abstract: An embodiment of the invention is an apparatus having a cleaning tank 2, a megasonic energy source 3, and an intake pipe 6 where a membrane contactor 9 is coupled to the intake pipe 6 to change the concentration of nitrogen gas in the deionized water 8 contained in intake pipe 6 to a range between 5.4% to 54% of saturation. Another embodiment is a method of changing the concentration of nitrogen gas in deionized water 8 to a range between 5.4% to 54% of saturation.