Abstract: Treating a low-k dielectric layer (104) using a highly oxidizing wet solution (e.g., H2SO4) to improve patterning. Resist poisoning occurs due to an interaction between low-k films (104), such as OSG, and DUV resist (130,132). The wet treatment is performed to either pre-treat a low-k dielectric (104) before forming the pattern (130,132) or during a rework of the pattern (130,132) to reduce resist poisoning.

Abstract: A process for polishing a semiconductor wafer includes the steps of providing a plurality of wafers, forming a first layer, such as a barrier layer, over at least a portion of each wafer, and forming at least one layer including copper over at least a portion of each first layer. The process also includes the steps of providing a first polishing pad, providing a buffing pad, providing a plurality of operatively connected wafer carriers, and disposing a wafer within each of the wafer carriers. The process further includes the steps of disposing a first slurry composition on the first polishing pad and polishing a first wafer with the first polishing pad for a first length of time, in which the first polishing pad substantially removes the copper layer of the first wafer.

Abstract: A process for polishing a semiconductor wafer includes the steps of providing a plurality of wafers, forming a first layer, such as a barrier layer, over at least a portion of each wafer, and forming at least one layer including copper over at least a portion of each first layer. The process also includes the steps of providing a first polishing pad, providing a buffing pad, providing a plurality of operatively connected wafer carriers, and disposing a wafer within each of the wafer carriers. The process further includes the steps of disposing a first slurry composition on the first polishing pad and polishing a first wafer with the first polishing pad for a first length of time, in which the first polishing pad substantially removes the copper layer of the first wafer.

Abstract: Treating a low-k dielectric layer (104) using a highly oxidizing wet solution (e.g., H2SO4) to improve patterning. Resist poisoning occurs due to an interaction between low-k films (104), such as OSG, and DUV resist (130,132). The wet treatment is performed to either pre-treat a low-k dielectric (104) before forming the pattern (130,132) or during a rework of the pattern (130,132) to reduce resist poisoning.

Abstract: Intermetal level dielectrics comprise fluorinated polydimethylenenaphthalene derived from the following monomers wherein each of R.sub.1, R.sub.2, R.sub.3, and R.sub.4 is selected from the group consisting of H, F, and fluorocarbon groups ##STR1## The dielectric and oxides may be between metal lines. Fluorination of the polydimethylenenaphthalene lowers dielectric constant and increases working temperature.

Abstract: A intermetal level dielectrics with copolymers of parylene and cyclic siloxances (432, 482) between metal lines plus oxides (450, 490), and vapor deposition method for the copolymerization. Fluorination of the copolymers lowers dielectric constant and increases working temperature.

Abstract: A intermetal level dielectrics with fluorinated (co)polymers of parylene (142) between metal lines (112-120), and vapor deposition method for the (co)polymerization followed by fluorination of the (co)polymers.

Abstract: A semiconductor device comprising first and second interconnect levels (14) and (16) is described. Mixed polymeric intermetal dielectrics (46), (48) and (50) are used to separate conductive elements (22), (24), (26), (36) and (38), respectively. The intermetal dielectric bodies (46), (48) and (50) comprise a mixture of perfluorinated and non-fluorinated parylene.