Abstract: A semiconductor processing method of making electrical connection between an electrically conductive line and a node location includes, a) forming an electrically conductive line over a substrate, the substrate having an outwardly exposed silicon containing node location to which electrical connection is to be made, the line having an outer portion and an inner portion, the inner portion laterally extending outward from the outer portion and having an outwardly exposed portion, the inner portion having a terminus adjacent the node location, and b) electrically connecting the extending inner portion with the node location. An integrated circuit is also described. The integrated circuit includes a semiconductor substrate, a node location on the substrate, and a conductive line over the substrate which is in electrical communication with the node location. The conductive line includes an outer portion and an inner portion.

Abstract: A semiconductor processing method of making electrical connection between an electrically conductive line and a node location includes, a) forming an electrically conductive line over a substrate, the substrate having an outwardly exposed silicon containing node location to which electrical connection is to be made, the line having an outer portion and an inner portion, the inner portion laterally extending outward from the outer portion and having an outwardly exposed portion, the inner portion having a terminus adjacent the node location, and b) electrically connecting the extending inner portion with the node location. An integrated circuit is also described. The integrated circuit includes a semiconductor substrate, a node location on the substrate, and a conductive line over the substrate which is in electrical communication with the node location. The conductive line includes an outer portion and an inner portion.

Abstract: A thin film field effect transistor includes: a) a thin film channel region; b) a pair of opposing electrically conductive first and second source/drain regions adjacent the thin film channel region; c) a gate insulator and a gate positioned adjacent the thin film channel region for electrically energizing the channel region to switch on the thin film field effect transistor; d) the first source/drain region having a first thickness, the second source/drain region having a second thickness, the channel region having a third thickness; at least one of the first and second thicknesses being greater than the third thickness. Methods are disclosed for making thin field effect transistors.

Abstract: A method of forming an SRAM cell includes, a) providing a pair of pull-down gates having associated transistor diffusion regions operatively adjacent thereto, one of the diffusion regions of each pull-down gate being electrically connected to the other pull-down gate; b) providing a pair of pull-up resistor nodes for electrical connection with a pair of respective pull-up resistors, the pull-up nodes being in respective electrical connection with one of the pull-down gate diffusion regions and the other pull-down gate; c) providing a first electrical insulating layer outwardly of the resistor nodes; d) providing a pair of contact openings, with respective widths, through the first insulating layer to the pair of resistor nodes; e) providing a second electrical insulating layer over the first layer and to within the pair of contact openings to a thickness which is less than one-half the open widths; f) anisotropically etching the second electrical insulating layer to define respective electrical insulating ann

Abstract: A thin film field effect transistor includes: a) a thin film channel region; b) a pair of opposing electrically conductive first and second source/drain regions adjacent the thin film channel region; c) a gate insulator and a gate positioned adjacent the thin film channel region for electrically energizing the channel region to switch on the thin film field effect transistor; d) the first source/drain region having a first thickness, the second source/drain region having a second thickness, the channel region having a third thickness; at least one of the first and second thicknesses being greater than the third thickness. Methods are disclosed for making thin field effect transistors.

Abstract: An electrical interconnection method includes: a) providing two conductive layers separated by an insulating material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each conductive layer; c) depositing an electrically conductive material over the etched conductive layers and their respective sidewalls; and d) anisotropically etching the conductive material to define an electrically conductive sidewall link electrically interconnecting the two conductive layers. Such is utilizable to make thin film transistors and other circuitry.

Abstract: A thin film transistor includes: a) a thin film transistor layer comprising a source region, a channel region and a drain region; the thin film transistor layer further comprising a drain offset region positioned between the drain region and the channel region; b) the channel region being substantially polycrystalline and having a first average crystalline grain size; and c) the drain offset region being substantially polycrystalline and having a second average crystalline grain size, the second average crystalline grain size being larger than the first average crystalline grain size. A method for forming such a construction using polycrystalline materials, preferably polysilicon, and an amorphizing silicon implant with subsequent recrystallization is also disclosed.

Abstract: A method of forming a field effect transistor includes, a) providing a silicon substrate having impurity doping of a first conductivity type; b) providing source and drain diffusion regions of a second conductivity type within the silicon substrate, the source region and the drain region being spaced from one another to define a channel region therebetween within the silicon substrate; c) providing a gate relative to the silicon substrate operatively adjacent the channel region; and d) providing respective ohmic electrical contacts to the source region and the drain region, the electrical contact to the source region comprising a substrate leaking junction, the electrical connection to the drain region not comprising a substrate leaking junction. A field effect transistor is also disclosed.

Abstract: A thin film transistor includes: a) a thin film transistor layer comprising a source region, a channel region and a drain region; the thin film transistor layer further comprising a drain offset region positioned between the drain region and the channel region; b) the channel region being substantially polycrystalline and having a first average crystalline grain size; and c) the drain offset region being substantially polycrystalline and having a second average crystalline grain size, the second average crystalline grain size being larger than the first average crystalline grain size. A method for forming such a construction using polycrystalline materials, preferably polysilicon, and an amorphizing silicon implant with subsequent recrystallization is also disclosed.

Abstract: The invention is a method for creating a portion of an integrated circuit on a semiconductor wafer. The invention comprises doping a substrate to form a doped well region having an opposite conductivity type than the substrate. Separate photomasking steps are used to define N-channel and P-channel metal oxide semiconductor (MOS) transistor gates. A trench is formed near the well without using additional masking steps. The trench improves the latch up immunity of the device. The invention is also the apparatus created by the method and comprises a trench positioned in the substrate to interrupt the conduction of minority carriers between two regions of the substrate. Thus, the invention improves latch up immunity without additional process complexity.

Abstract: A semiconductor processing method of forming a conductive polysilicon line relative to a substrate includes, a) providing a line of silicon on a substrate, the line having an outer top surface and outwardly exposed opposing outer sidewall surfaces, the line ultimately comprising conductively doped polysilicon; b) masking the line outer top surface with a masking material; c) with the masking material in place, depositing a metal layer atop the substrate and over the masking material and the outwardly exposed line outer sidewall surfaces; d) annealing the line to impart a silicidation reaction between the metal and opposing silicon sidewalls to form opposing metal silicide runners extending along the line sidewalls, the masking material preventing a silicidation reaction from occurring between the metal and line outer top surface; and e) stripping the metal layer from atop the line. Such a line is preferably used as a bottom gate for a thin film transistor.

Abstract: A method of forming a thin film transistor includes, a) forming a thin film transistor layer of semiconductive material; b) providing a gate operatively adjacent the thin film transistor layer; c) forming at least one electrically conductive sidewall spacer over at least one lateral edge of the gate, the spacer being electrically continuous therewith; and d) providing a source region, a drain region, a drain offset region, and a channel region in the thin film transistor layer; the drain offset region being positioned operatively adjacent the one electrically conductive sidewall spacer and being gated thereby. The spacer is formed by anisotropically etching a spacer forming layer.

Abstract: A semiconductor processing method of forming a conductive polysilicon line relative to a substrate includes, a) providing a line of silicon on a substrate, the line having an outer top surface and outwardly exposed opposing outer sidewall surfaces, the line ultimately comprising conductively doped polysilicon; b) masking the line outer top surface with a masking material; c) with the masking material in place, depositing a metal layer atop the substrate and over the masking material and the outwardly exposed line outer sidewall surfaces; d) annealing the line to impart a silicidation reaction between the metal and opposing silicon sidewalls to form opposing metal silicide runners extending along the line sidewalls, the masking material preventing a silicidation reaction from occurring between the metal and line outer top surface; and e) stripping the metal layer from atop the line. Such a line is preferably used as a bottom gate for a thin film transistor.

Abstract: A method of forming a field effect transistor includes, a) providing a silicon substrate having impurity doping of a first conductivity type; b) providing source and drain diffusion regions of a second conductivity type within the silicon substrate, the source region and the drain region being spaced from one another to define a channel region therebetween within the silicon substrate; c) providing a gate relative to the silicon substrate operatively adjacent the channel region; and d) providing respective ohmic electrical contacts to the source region and the drain region, the electrical contact to the source region comprising a substrate leaking junction, the electrical connection to the drain region not comprising a substrate leaking junction. A field effect transistor is also disclosed.

Abstract: A thin film transistor includes a thin film transistor layer having a source region, a channel region and a drain region. In one implementation, a gate of the transistor is disposed laterally proximate the thin film channel region and comprises an annulus which laterally encircles the laterally proximate thin film channel region. In another implementation, a channel region of a thin film transistor extends elevationally away from a substrate. Source and drain regions are operatively associated with the channel region and are elevationally spaced therealong and apart from one another. A gate is disposed over the substrate and laterally proximate the channel region.

Abstract: A method of forming a thin film transistor includes, a) forming a thin film transistor layer of semiconductive material; b) providing a gate operatively adjacent the thin film transistor layer; c) forming at least one electrically conductive sidewall spacer over at least one lateral edge of the gate, the spacer being electrically continuous therewith; and d) providing a source region, a drain region, a drain offset region, and a channel region in the thin film transistor layer; the drain offset region being positioned operatively adjacent the one electrically conductive sidewall spacer and being gated thereby. The spacer is formed by anisotropically etching a spacer forming layer.

Abstract: A thin film field effect transistor includes: a) a thin film channel region; b) a pair of opposing electrically conductive first and second source/drain regions adjacent the thin film channel region; c) a gate insulator and a gate positioned adjacent the thin film channel region for electrically energizing the channel region to switch on the thin film field effect transistor; d) the first source/drain region having a first thickness, the second source/drain region having a second thickness, the channel region having a third thickness; at least one of the first and second thicknesses being greater than the third thickness. Methods are disclosed for making thin field effect transistors.

Abstract: A semiconductor processing method of making electrical connection between an electrically conductive line and a node location includes, a) forming an electrically conductive line over a substrate, the substrate having an outwardly exposed silicon containing node location to which electrical connection is to be made, the line having an outer portion and an inner portion, the inner portion laterally extending outward from the outer portion and having an outwardly exposed portion, the inner portion having a terminus adjacent the node location, and b) electrically connecting the extending inner portion with the node location. An integrated circuit is also described. The integrated circuit includes a semiconductor substrate, a node location on the substrate, and a conductive line over the substrate which is in electrical communication with the node location. The conductive line includes an outer portion and an inner portion.

Abstract: A static memory cell is described which has cross coupled pulldown transistors and dual access transistors. The memory cell is fabricated such that balanced current paths are formed through the two pulldown transistors. A single word line is used to activate the access transistors which couple the memory cell to complementary bit lines. The memory cells, as viewed in a plan view, have the single word line and gates of the pulldown transistors fabricated in parallel.

Abstract: A method of forming BiCMOS circuitry includes, i) conducting a first common second conductivity type implant into, a) a first substrate area to comprise a second conductivity type well for a first area first conductivity type FET, and b) a third substrate area to comprise one of a bipolar transistor second conductivity type collector or emitter region; ii) providing field oxide regions and active area regions within first, second and third areas of the substrate; iii) conducting a first common first conductivity type implant into, a) the second substrate area to comprise a first conductivity type channel stop region beneath field oxide in the second area, and b) the third substrate area to comprise the bipolar transistor base; and iv) conducting a second common second conductivity type implant into, a) at least one of the first or the second substrate areas to comprise at least one of a source/drain implant or a graded junction implant for at least one of the first or second conductivity type FETs, and b) the