Abstract: A thin film field effect transistor includes: a) a thin film channel region; b) a pair of opposing electrically conductive first and second source/drain regions adjacent the thin film channel region; c) a gate insulator and a gate positioned adjacent the thin film channel region for electrically energizing the channel region to switch on the thin film field effect transistor; d) the first source/drain region having a first thickness, the second source/drain region having a second thickness, the channel region having a third thickness; at least one of the first and second thicknesses being greater than the third thickness. Methods are disclosed for making thin field effect transistors.

Abstract: A method of forming integrated circuitry includes, a) providing a pair of spaced and adjacent electrically conductive elongated lines; and b) providing electrically insulative material over the pair of spaced lines in a manner which leaves an elongated void between the lines, the elongated void being top sealed along its substantial elongated length. Preferably, the electrically insulative material is provided by depositing electrically insulative material over the pair of lines in a manner which produces a retrograde cross-sectional profile of the insulating material relative to the respective line sidewalls and which leaves an elongated top sealed void within the insulating material between the lines, the elongated void being open at at least one end. The void at the one end is subsequently sealed.

Abstract: A thin film field effect transistor includes: a) a thin film channel region; b) a pair of opposing electrically conductive first and second source/drain regions adjacent the thin film channel region; c) a gate insulator and a gate positioned adjacent the thin film channel region for electrically energizing the channel region to switch on the thin film field effect transistor; d) the first source/drain region having a first thickness, the second source/drain region having a second thickness, the channel region having a third thickness; at least one of the first and second thicknesses being greater than the third thickness. Methods are disclosed for making thin field effect transistors.

Abstract: A method of forming BiCMOS circuitry includes, i) conducting a first common second conductivity type implant into, a) a first substrate area to comprise a second conductivity type well for a first area first conductivity type FET, and b) a third substrate area to comprise one of a bipolar transistor second conductivity type collector or emitter region; ii) providing field oxide regions and active area regions within first, second and third areas of the substrate; iii) conducting a first common first conductivity type implant into, a) the second substrate area to comprise a first conductivity type channel stop region beneath field oxide in the second area, and b) the third substrate area to comprise the bipolar transistor base; and iv) conducting a second common second conductivity type implant into, a) at least one of the first or the second substrate areas to comprise at least one of a source/drain implant or a graded junction implant for at least one of the first or second conductivity type FETs, and b) the

Abstract: The disclosure includes preferred semiconductor transistor devices utilizing thin film transistors, as well as preferred methods of forming such devices. Specifically, a bottom thin film transistor gate is formed having a top surface. An insulating filler is provided adjacent the thin film transistor gate to an elevation at least as high as the thin film transistor gate top surface, and subsequently levelled to provide generally planar insulating surfaces adjacent the thin film transistor gate. The planar insulating surfaces are substantially coplanar with the thin film transistor gate top surface. A planar semiconductor thin film is then formed over the thin film transistor gate and over the adjacent planar insulating surfaces. The thin film is doped to form source and drain regions of a thin film transistor which is bottom gated by the thin film transistor gate.

Abstract: In a microcircuit device such as a memory chip, where a bank of state devices such as fuses and anti-fuses determines the enabling and disabling of redundant circuitry, a scheme for blowing one or more state devices by applying a programming voltage through a switching circuit comprising thin film transistors (TFTs) which are not damaged by the device blowing, programming voltage. The TFTs can be activated by a low voltage enable signal provided by a state device designator logic module.

Abstract: Disclosed are methods of forming resistors and diodes from semiconductive material, and static random access memory (SRAM) cells incorporating resistors, and to integrated circuitry incorporating resistors and diodes. A node to which electrical connection is to be made is provided. An electrically insulative layer is provided outwardly of the node. An opening is provided in the electrically insulative layer over the node. The opening is filled with semiconductive material which depending on configuration serves as one or both of a vertically elongated diode and resistor.

Abstract: A method of forming a thin film transistor of a first conductivity type includes, a) providing a thin film transistor layer of semiconductive material; b) first masking the thin film transistor layer to mask a desired drain offset region while leaving a desired channel region exposed; c) with the first masking in place, doping the exposed channel region with a conductivity enhancing impurity of a second type; d) second masking the thin film transistor layer to mask the channel region and the drain offset region and leave desired opposing source/drain regions exposed; and e) with the second masking in place, doping the exposed source/drain regions with a conductivity enhancing impurity of the first type.

Abstract: A static memory cell is described which has cross coupled pulldown transistors and dual access transistors. The memory cell is fabricated such that balanced current paths are formed through the two pulldown transistors. A single word line is used to activate the access transistors which couple the memory cell to complementary bit lines. The memory cells, as viewed in a plan view, have the single word line and gates of the pulldown transistors fabricated in parallel.

Abstract: A variable resistance material-based memory cell is disclosed for use in an electronic memory. The memory cell includes a MOS diode for delivering large amounts of current to the variable resistance material, as needed during programming of the memory cell. In one embodiment, a buried contact under the gate is used as the drain of the device. The buried contact allows formation of a very short channel, causing a "snapback" phenomenon in the MOS diode and thereby greatly increasing the amount of current flow across the device. This buried contact construction has the additional advantage of reducing the area needed for the memory cell. Additionally, the processing is simple and may be performed using the same techniques normally used during the fabrication of electronic memories.

Abstract: A thin film field effect transistor includes: a) a thin film channel region; b) a pair of opposing electrically conductive first and second source/drain regions adjacent the thin film channel region; c) a gate insulator and a gate positioned adjacent the thin film channel region for electrically energizing the channel region to switch on the thin film field effect transistor; d) the first source/drain region having a first thickness, the second source/drain region having a second thickness, the channel region having a third thickness; at least one of the first and second thicknesses being greater than the third thickness. Methods are disclosed for making thin field effect transistors.

Abstract: A thin film transistor includes a thin film transistor layer having a source region, a channel region and a drain region. In one implementation, a gate of the transistor is disposed laterally proximate the thin film channel region and comprises an annulus which laterally encircles the laterally proximate thin film channel region. In another implementation, a channel region of a thin film transistor extends elevationally away from a substrate. Source and drain regions are operatively associated with the channel region and are elevationally spaced therealong and apart from one another. A gate is disposed over the substrate and laterally proximate the channel region.

Abstract: A semiconductor processing method of forming a conductive polysilicon line relative to a substrate includes, a) providing a line of silicon on a substrate, the line having an outer top surface and outwardly exposed opposing outer sidewall surfaces, the line ultimately comprising conductively doped polysilicon; b) masking the line outer top surface with a masking material; c) with the masking material in place, depositing a metal layer atop the substrate and over the masking material and the outwardly exposed line outer sidewall surfaces; d) annealing the line to impart a silicidation reaction between the metal and opposing silicon sidewalls to form opposing metal silicide runners extending along the line sidewalls, the masking material preventing a silicidation reaction from occurring between the metal and line outer top surface; and e) stripping the metal layer from atop the line. Such a line is preferably used as a bottom gate for a thin film transistor.

Abstract: The method of the present invention introduces a method of forming conductively doped contacts on a supporting substrate in a semiconductor device that minimizes the lateral out-diffusion of the conductive dopants and also provides for a low resistive contact by the steps of: preparing a conductive area to accept contact formation; forming a phosphorus insitu doped polysilicon layer over the conductive area; forming an arsenic insitu doped polysilicon layer over the phosphorus insitu doped polysilicon layer, wherein the two insitu doped polysilicon layers are deposited one after another in separate deposition steps; and annealing the layers at a temperature range of approximately 900.degree.-1100.degree. C. thereby, resulting in sufficient thermal treatment to allow phosphorus atoms to break up a first interfacial silicon dioxide layer formed between the conductive area and the phosphorus insitu doped polysilicon layer.

Abstract: The invention is a method for creating a portion of an integrated circuit on a semiconductor wafer. The invention comprises doping a substrate to form a doped well region having an opposite conductivity type than the substrate. Separate photomasking steps are used to define N-channel and P-channel metal oxide semiconductor (MOS) transistor gates. A trench is formed near the well without using additional masking steps. The trench improves the latch up immunity of the device. The invention is also the apparatus created by the method and comprises a trench positioned in the substrate to interrupt the conduction of minority carriers between two regions of the substrate. Thus, the invention improves latch up immunity without additional process complexity.

Abstract: A semiconductor processing method of providing a polysilicon layer atop a semiconductor wafer comprises the following sequential steps: a) depositing a first layer of arsenic atop a semiconductor wafer; b) depositing a second layer of silicon over the arsenic layer, the second layer having an outer surface; c) first annealing the wafer at a temperature of at least about 600.degree. C. for a time period sufficient to impart growth of polycrystalline silicon grains in the second layer and providing a predominately polysilicon second layer, the first annealing step imparting diffusion of arsenic within the second layer to promote growth of large polysilicon grains; and d) with the second layer outer surface being outwardly exposed, second annealing the wafer at a temperature effectively higher than the first annealing temperature for a time period sufficient to outgas arsenic from the polysilicon layer.

Abstract: The invention is directed to a thin film transistor (TFT) fabricated by using a planarized poly plug as the bottom gate for use in any integrated circuit and in particular a static random access memory (SRAM). The TFT is used in an SRAM device to form a planarized SRAM cell comprising: a pulldown transistor having a control gate and source/drain terminals; a planarized insulating layer having grooves therein, each groove providing access to an underlying conductive material; a planarized conductive plug residing inside each groove, whereby a first conductive plug forms a thin film transistor gate connecting to an to an adjacent inverter and a second conductive plug provides connection to the gate of the pulldown device; a gate dielectric overlying the first planarized conductive plug; and a patterned semiconductive layer doped such that a channel region aligns to each thin film transistor gate and a source/drain region aligns to each side of the channel region is formed.

Abstract: A semiconductor processing method of forming a buried contact to a substrate region includes, a) providing a stress relief layer over a bulk semiconductor substrate; b) etching the stress relief layer to expose a desired buried contact area of the substrate; c) masking over the stress relief layer and over the desired buried contact area; d) with the masking in place, exposing the substrate to oxidation conditions effective to grow field oxide regions in unmasked areas of the substrate; e) after forming the field oxide regions, removing the masking from the substrate and effectively leaving the buried contact area exposed; f) providing a layer of electrically conductive material over field oxide and exposed buried contact area; and g) patterning the conductive material layer into a conductive line which overlies both field oxide and the buried contact area.

Abstract: The present invention develops a process for forming dual conductive wells in a silicon substrate for an integrated circuit by: forming an oxide layer on the silicon substrate; patterning an oxidation barrier layer on the oxide layer, thereby defining active areas for active devices; introducing first p-type conductive impurities into the silicon substrate thereby forming at least one p-type conductively doped well region; masking over the p-type conductively doped well region; introducing n-type conductive impurities into the silicon substrate thereby forming at least one n-type conductively doped well region; removing the masking; forming oxide regions in areas not covered by the patterned oxidation barrier layer; and forcing the p-type and n-type conductive impurities further into the silicon substrate thereby forming the dual well regions, the well regions having adequate conductive depth to provide for the formation of the active devices.

Abstract: A method of forming BiCMOS circuitry includes, i) conducting a first common second conductivity type implant into, a) a first substrate area to comprise a second conductivity type well for a first area first conductivity type FET, and b) a third substrate area to comprise one of a bipolar transistor second conductivity type collector or emitter region; ii) providing field oxide regions and active area regions within first, second and third areas of the substrate; iii) conducting a first common first conductivity type implant into, a) the second substrate area to comprise a first conductivity type channel stop region beneath field oxide in the second area, and b) the third substrate area to comprise the bipolar transistor base; and iv) conducting a second common second conductivity type implant into, a) at least one of the first or the second substrate areas to comprise at least one of a source/drain implant or a graded junction implant for at least one of the first or second conductivity type FETs, and b) the