Abstract: The invention is directed to a thin film transistor (TFT) fabricated by using a recessed planarized poly plug as the bottom gate and a recessed planarized poly plug for the TFT drain connecting region. The TFT of the present invention can be used in any integrated circuit that uses such devices and in particular as a pullup device in a static random access memory (SRAM). The invention is directed to a process to fabricate a thin film transistor (TFT) having LDDs and/or high resistive regions (loads) that are self-aligned to a recessed plug that is used as the bottom gate for the TFT.

Abstract: A semiconducting wafer has an active area and first and second field oxide regions adjacent opposite sides of the active area. A first poly layer is deposited to form a first landing pad member electrically contacting the active area and overlapping the first field oxide region. Then an insulating oxide layer is deposited, followed by a second poly layer to form a second landing pad member overlapping the first landing pad member and the second field oxide region. A contact etch is performed with the landing pad members acting as an etch stop. A contact is deposited to electrically contact the landing pad members.

Abstract: A buried contact is formed in a substrate implantation of phosphorous or arsenic through a window cut into the insulating silicon oxide layer and a superimposed thin silicon layer. The photoresist used to etch the window is cut back a limited amount prior to implantation. The peripheral margin of the buried contact implanted through the exposed part of the thin layer of silicon lowers the threshold voltage of any parasitic MOS device which may be created between the buried contact and the remote N+source or drain structure.

Abstract: Disclosed herein is a method and structure which connects a thin film transistor active region to a semiconductor region of a different conductivity type and which shunts the parasitic diode formed between the two regions. A transistor gate is formed on a semiconductor substrate. A thin film of polysilicon is provided over the transistor gate to form thin film active regions and a thin film channel region. The thin film active regions are doped with an impurity of a first conductivity type. A semiconductor region of a second conductivity type is also formed over the semiconductor substrate, with the thin polysilicon film forming a connecting region which overlies and contacts the semiconductor region. The connecting region is doped to a second conductivity type to create a parasitic diode in the thin polysilicon film rather than between the connecting region and the thin polysilicon film.

Abstract: The invention is directed to improving trench isolation between active devices by using gated sidewalls. In a first embodiment, trenches are etched into the substrate and a thin oxide film is formed to passivate the trench sidewalls and serve as a sidewall gate oxide. The oxide is removed from the bottom of the trench while leaving the sidewall oxide intact. A thin poly layer is formed into the trench so that the thin poly does not completely fill the trench, yet the thin poly film will overlie the oxide sidewalls and make contact to the exposed substrate at the bottom of the trench. The trench is then completely filled with a conformal oxide that is planarized. The planarized oxide is etched during thermal oxide etch and a sacrificial oxide is grown. Following threshold adjust implants, the sacrificial oxide is removed and the final gate sidewall oxide is formed.

Abstract: Self-aligned contacts are formed between a first layer of material which can be oxidized, such as polycrystalline silicon (poly 1), and a second layer of material such as metal or polycrystalline silicon (poly 2). A patterned layer of material, such as nitride, that prevents the first layer from oxidizing is deposited over the poly 1 layer. The exposed poly 1 material is oxidized, while the poly 1 material covered by the nitride is protected from oxidization. The nitride is removed and another layer of conductive material is formed, and thus contacts the poly 1 layer which was protected from oxidation, while the oxide insulates the other poly 1 areas.

Abstract: A low cost active P-channel load for use in semiconductor devices is developed. The active P-channel load may be used in a variety of designs, such as functioning as a pullup device in integrated circuits and more specifically for use as a pullup resistor in SRAM devices. The P-channel load is built overlying an active NMOS device and not only takes up less die space but also allows for a simple process to construct the P-channel load. This P-channel device is easily incorporated into an SRAM process flow to build an SRAM cell made up of active NMOS devices that utilize the P-channel devices as pullups.

Abstract: A self-aligned vertical intrinsic resistance for use in semiconductor devices is developed. The self-aligned vertical intrinsic resistance may be used in a variety of designs, such as functioning as a pullup device in integrated circuits and more specifically for use as a pullup resistor in SRAM devices. The vertical positioning of the intrinsic resistance not only takes up less die space but also allows for a simple process to construct the resistance by eliminating a photomask step that is normally required prior to implanting an intrinsic resistance used in conventional fabrication processes.

Abstract: A method for fabricating a high value, vertically integrated resistor begins with an integrated circuit having an unpassivated upper surface that includes designated circuit nodes to be placed in series with the vertical resistor. A layer of passivating material such as boro-phospho silicate glass is deposited on the upper surface of the integrated circuit. Polysilicon vias are formed that extend through the passivating layer and form an electrical ohmic contact with each designated circuit node. The polysilicon vias are subsequently ion implanted with oxygen or nitrogen to increase the resistance thereof to the final desired resistance, which can be greater than 100 megohms, and as much as a gigohm or a terohm. Finally, the vertical resistor is contacted with a metal layer formed on the surface of the passivating layer.

Abstract: The present invention introduces a method to fabricate a self-aligning active PMOS device fabricated on top of an NMOS active device, thereby forming a CMOS inverter having a gate electrode being common to the two active devices. This fabrication technique provides for a less expensive method to form a CMOS inverter that may be used simply as an inverter or as a building block to construct an SRAM cell which results in reduced manufacturing cost compared to that of conventional CMOS fabrication processes. Standard transistors are formed in a starting substrate with a poly gate sandwich structure having its top layer serving as the channel region of the active PMOS of the present invention. Next, an inter-poly dielectric is deposited and a buried contact are formed to allow a subsequently deposited P+ poly of the PMOS device to make connection to the substrate diffusion areas. This P+ layer of poly is planarized to clear the poly over the NMOS poly gates and exposed the underlying oxide.

Abstract: Disclosed herein is a thin film field effect transistor and a method for producing such a thin film transistor. The thin film transistor has a transistor gate and thin film active and channel regions. The transistor gate has a top surface and sidewalls which are coated with a thin gate insulating layer. A thin semiconductor film is provided over the transistor gate and thin gate insulating layer to form a conductively doped thin film channel region and conductively doped thin film active regions. The thin film channel region contacts the thin gate insulating layer opposite the transistor gate top surface and opposite the sidewalls. The transistor gate sidewalls in operation gate the opposite thin film channel region through the thin gate insulating layer. The thin film field effect transistor can be fabricated over an underlying MOSFET to form a CMOS inverter with the transistor gate being common to both the thin film transistor and the MOSFET.

Abstract: A low cost active P-channel load for use in semiconductor devices is developed. The active P-channel load may be used in a variety of designs, such as functioning as a pullup device in integrated circuits and more specifically for use as a pullup resistor in SRAM devices. The P-channel load is built overlying an active NMOS device and not only takes up less die space but also allows for a simple process to construct the P-channel load. This P-channel device is easily incorporated into an SRAM process flow to build an SRAM cell made up of active NMOS devices that utilize the P-channel devices as pullups.

Abstract: A method of forming isolation trenches and mesa areas in a semiconductor substrate and of forming FETs in the mesa areas is disclosed. The method includes providing a first oxide layer, a first undoped polysilicon layer, and an etch stop layer on a silicon substrate. Isolation trenches and mesa areas are then defined by etching the substrate. A second oxide layer is provided to fill the isolation trenches, and is subsequently etched to remove second layer oxide above the mesa areas, thus exposing the first polysilicon layer. The method further comprises providing a second, conductively doped polysilicon layer over the exposed first polysilicon layer, wherein the first polysilicon layer is autodoped by the second polysilicon layer in a subsequent step. The first and second layers of polysilicon are patterned and etched to define FET gates in the mesa areas, with the first oxide layer beneath the first polysilicon layer being utilized as gate oxide.

Abstract: A self-aligned vertical intrinsic resistance for use in semiconductor devices is developed. The self-aligned vertical intrinsic resistance may be used in a variety of designs, such as functioning as a pullup device in integrated circuits and more specifically for use as a pullup resistor in SRAM devices. The vertical positioning of the intrinsic resistance not only takes up less die space but also allows for a simple process to construct the resistance by eliminating a photomask step that is normally required prior to implanting an intrinsic resistance used in conventional fabrication processes.

Abstract: Described is a method of forming a self-aligned contact to an underlying structure with fewer critical patterning steps. The invention uses an isotropic oxygen plasma etch of a resist layer and a subsequent oxide etch to expose an underlying conductive layer such as doped polycrystalline silicon. A second conductive layer formed thereupon contacts the exposed first conductive layer.

Abstract: An SRAM wafer is conventionally fabricated through the definition of the gate poly. The PMOS oxide is then applied in a layer that uniformly covers the surface and sidewalls of the gate poly, then the interpoly contacts are patterned and etched and the NMOS S/D's are implanted. The PMOS load poly is deposited, again in a layer that uniformly covers the PMOS oxide over the surface and sidewalls of the gate poly. Oxide spacers are formed on the PMOS poly along the gate poly sidewalls, and a P+ implantation forms the PMOS sources and drains. The oxide spacers protect an L-shaped region along the poly gate sidewall from the P+ implant, thus defining PMOS load channels on either side of the gate poly that are gated by the gate poly sidewalls. The foot of the L on one side and the extension of the L above the gate poly on the other create gate/drain offsets that reduce I(off). Optionally, a gate poly/oxide stack may be used to enlarge one of the gate/drain offsets.

Abstract: A method for fabricating a high value, vertically integrated resistor begins with an integrated circuit having an unpassivated upper surface that includes designated circuit nodes to be placed in series with the vertical resistor. A layer of passivating material such as boro-phospho silicate glass is deposited on the upper surface of the integrated circuit. Polysilicon vias are formed that extend through the passivating layer and form an electrical ohmic contact with each designated circuit node. The polysilicon vias are subsequently ion implanted with oxygen or nitrogen to increase the resistance thereof to the final desired resistance, which can be greater than 100 megohms, and as much as a gigohm or a terohm. Finally, the vertical resistor is contacted with a metal layer formed on the surface of the passivating layer.

Abstract: A method for forming lower levels of metal in multilevel interconnects involves initial formation of a poly-metal dielectric layer having grooves and contact holes, subsequent deposition of a covering layer of metal, masking of the covering layer and etching to produce protruding pillars, and addition of an intermetal dielectric layer surrounding the pillars. The process steps produce a metal level having integral studs or posts, conduction strips and contacts.