Abstract: A circuit board according to an embodiment includes a first insulating layer; a second insulating layer disposed on the first insulating layer and including a cavity; and a plurality of pads disposed on the first insulating layer and having top surfaces exposed through the cavity; wherein the cavity of the second insulating layer includes: a bottom surface positioned higher than a top surface of the first insulating layer; and an inner wall extending from the bottom surface, wherein the inner wall is perpendicular to top or bottom surface of the second insulating layer, wherein the bottom surface of the cavity includes: a first bottom surface positioned lower than a top surface of the pad and positioned outside an arrangement region of the plurality of pads; and a second bottom surface positioned lower than the top surface of the pad and positioned inside the arrangement region of the plurality of pads, and wherein a height of the first bottom surface is different from a height of the second bottom surface.

Abstract: A resin composition for a semiconductor package according to an embodiment includes a resin composition that is a composite of a resin and a filler disposed in the resin, wherein the filler includes at least one concave portion provided on a surface, wherein a content of the filler has a range of 10 vol. % to 40 vol % of a total volume of the resin composition, and wherein a porosity corresponds to a volume occupied by the concave portion in a total volume of the filler and has a range of 20% to 35%.

Abstract: A circuit board according to an embodiment includes: an insulating layer including first to third regions; an outer layer circuit pattern disposed on an upper surface of the first to third regions of the insulating layer; and a solder resist including a first part disposed on the first region of the insulating layer, a second part disposed on the second region, and a third part disposed on the third region, wherein the outer layer circuit pattern includes: a first trace disposed on an upper surface of the first region of the insulating layer; and a second trace disposed on an upper surface of the third region of the insulating layer; wherein a height of the first trace is different from a height of the second trace; and an upper surface of the first part of the solder resist is positioned lower than an upper surface of the first trace.

Abstract: A circuit board according to an embodiment comprises: an insulation layer; a circuit pattern disposed on the upper surface or under the lower surface of the insulation layer; and a buffer layer disposed on at least one surface of the upper surface and the lower surface of the insulation layer, wherein the buffer layer includes carbon, nitrogen, and oxygen, the ratio of the nitrogen to the carbon ((carbon/nitrogen)*100) is 5 to 15, and the ratio of the oxygen to the carbon ((carbon/oxygen)*100) is 15 to 30.

Abstract: A resin coated copper according to an embodiment includes: an insulating layer including a resin and a filler dispersed in the resin; and a copper foil layer disposed on the insulating layer, wherein the insulating layer has a plurality of pores formed on a surface in contact with the copper foil layer, and the plurality of pores have a width of 200 nm to 350 nm.

Abstract: An electrophoretic particle according to an embodiment contains carbon black, and the electrophoretic particle comprises: a core portion; and a shell portion disposed to surround the outer surface of the core portion, wherein a protrusion portion is formed on the surface of the core portion, the core portion has a chromaticity index of 2 or less, the core portion has a light absorption rate of 90% to 99%, and the particle diameter of the electrophoretic particles is 50 nm to 800 nm.

Abstract: A printed circuit board according to one embodiment of the present invention comprises an insulation board and a plurality of metal electrodes disposed on the insulation board, wherein: the plurality of metal electrodes include a first electrode and a second electrode; the first electrode includes a first surface parallel to an upper surface of the insulation board, a second surface facing the first surface, a first side surface disposed between the first surface and the second surface, and a second side surface facing the first side surface; a part of the first side surface and a part of the second side surface protrude toward the outside of the first electrode in the direction parallel to the upper surface of the insulation board; the first side surface protrudes farther in an area adjacent to the first surface than in an area adjacent to the second surface; and the second side surface protrudes farther in the area adjacent to the second surface than in the area adjacent to the first surface.

Abstract: A circuit board according to one embodiment comprises a first insulation layer, a circuit pattern on the first insulation layer, and a second insulation layer on the circuit pattern, wherein a heat transfer member is arranged inside the first insulation layer and/or the second insulation layer, and the heat transfer member is arranged while coming in contact with a side surface of the insulation layer.

Abstract: A circuit board according to an embodiment includes an insulating layer; and a circuit pattern disposed on the insulating layer, wherein the circuit pattern includes a copper foil layer disposed on the insulating layer, a first plating layer disposed on the copper foil layer, and a second plating layer disposed on the first plating layer, and wherein the copper foil layer has a thickness in a range of 2 ?m to 5 ?m.

Abstract: A printed circuit board according to one embodiment of the present invention comprises an insulation board and a plurality of metal electrodes disposed on the insulation board, wherein: the plurality of metal electrodes include a first electrode and a second electrode; the first electrode includes a first surface parallel to an upper surface of the insulation board, a second surface facing the first surface, a first side surface disposed between the first surface and the second surface, and a second side surface facing the first side surface; a part of the first side surface and a part of the second side surface protrude toward the outside of the first electrode in the direction parallel to the upper surface of the insulation board; the first side surface protrudes farther in an area adjacent to the first surface than in an area adjacent to the second surface; and the second side surface protrudes farther in the area adjacent to the second surface than in the area adjacent to the first surface.

Abstract: A method of fabricating a wafer according to the embodiment comprises the steps of growing an wafer on a surface of the wafer in a growth temperature; and cooling the wafer after the wafer has been grown, wherein a stepwise cooling is performed when cooling the wafer.

Abstract: Disclosed are a hot plate and a method of manufacturing the same. The method includes the steps of preparing a first barrier layer, laminating a first heat transfer layer on the first barrier layer, and laminating a second barrier layer on the first heat transfer layer. The first barrier layer or the second barrier layer includes a plurality of first sub-nano-barrier layers and a plurality of second sub-nano-barrier layers. The hot plate includes a first barrier layer, a first heat transfer layer on the first barrier layer, and a second barrier layer on the first heat transfer layer. The first barrier layer or the second barrier layer includes a plurality of first sub-nano-barrier layers and a plurality of second sub-nano-barrier layers.

Abstract: A semiconductor device according to the embodiment comprises a base substrate; patterns on the base substrate; and an epitaxial layer on the base substrate, wherein the epitaxial layer is formed on a surface of the substrate exposed among the patterns. A method for growing a semiconductor crystal comprises the steps of cleaning a silicon carbide substrate; forming patterns on the silicon carbide substrate; and forming an epitaxial layer on the silicon carbide substrate.

Abstract: A method for fabricating a wafer according to the embodiment comprises the steps of depositing an epi layer in an epi deposition part; transferring the wafer to an annealing part connected to the epi deposition part; annealing the wafer in the annealing part; transferring the wafer to a cooling part connected to the annealing part; and cooling the wafer in the cooling part, wherein the depositing of the wafer, the annealing of the wafer and the cooling of the wafer are continuously performed. An apparatus for fabricating a wafer according to the embodiment comprises an epi deposition part; an annealing part connected to the epi deposition part; and a cooling part connected to the annealing part.

Abstract: Disclosed is a method of manufacturing a thin film, the method including: growing an epitaxial layer on a surface of a wafer at a growth temperature, wherein the growing of the epitaxial layer comprises controlling a defect present on a surface of the wafer. Also, disclosed is a wafer including: a substrate; and an epitaxial layer located on the substrate, wherein a basal dislocation density of the epitaxial layer is equal to or less than 1/cm2.

Abstract: A semiconductor device comprises a base substrate, a pattern on the base substrate, a buffer layer on the base substrate, and an epitaxial layer on the buffer. The pattern is a self-assembled pattern. A method for growing a semiconductor crystal comprises cleaning a silicon carbide substrate, forming a self-assembled pattern on the silicon carbide substrate, forming a buffer layer on the silicon carbide substrate, and forming an epitaxial layer on the buffer layer. A semiconductor device comprises a base substrate comprising a pattern groove and an epitaxial layer on the base substrate. A method for growing a semiconductor crystal comprises cleaning a silicon carbide substrate, forming a self-assembled projection on the silicon carbide substrate, forming a pattern groove in the silicon carbide, and forming an epitaxial layer on the silicon carbide.

Abstract: An apparatus for removing a defect according to the embodiment includes an image processing part for observing a surface of a substrate; a layer forming part for forming a layer on the surface of the substrate; and a humidity controlling part for controlling humidity in a chamber in which the substrate is placed. A method for removing a defect according to the embodiment includes detecting the defect on a surface of a substrate; forming an oxide layer by oxidizing the defect; and removing the oxide layer. A method for removing a defect according to another embodiment includes forming an oxide layer on an entire surface of a substrate; and removing the oxide layer to remove the defect.

Abstract: A method for fabricating a silicon carbide epitaxial wafer according to the embodiment includes introducing a carbon source and a silicon source into a reactor in which a silicon carbide wafer is provided; heating the reactor; and adjusting an amount of the silicon source or the carbon source introduced into the reactor. A silicon carbide epitaxial wafer according to the embodiment includes a silicon carbide epitaxial layer having a surface roughness of 0.3 nm or less.

Abstract: Disclosed is a deposition apparatus. The deposition apparatus comprises a susceptor into which reaction gas is introduced; a holder supporting a substrate in the susceptor; and a rotating driver for rotating the holder.

Abstract: Disclosed is a method of manufacturing a thin film, the method including: growing an epitaxial layer on a surface of a wafer at a growth temperature, wherein the growing of the epitaxial layer comprises controlling a defect present on a surface of the wafer. Also, disclosed is a wafer including: a substrate; and an epitaxial layer located on the substrate, wherein a basal dislocation density of the epitaxial layer is equal to or less than 1/cm2.