Abstract: A substrate transferring system may include a first transfer unit to transfer a substrate along a circular first orbit while rotating on a first axis perpendicular to a ground, and a second transfer unit to transfer a substrate along a circular second orbit while rotating on a second axis perpendicular to the ground, wherein the first orbit and the second orbit may overlap with each other at a first point, and at the first point, a substrate may be transferred from the first transfer unit to the second transfer unit or from the second transfer unit to the first transfer unit.

Abstract: Semiconductor devices are provided. A semiconductor device includes a gate structure and an adjacent contact. The semiconductor device includes a connector that is connected to the contact. In some embodiments, the semiconductor device includes a wiring pattern that is connected to the connector. Moreover, in some embodiments, the connector is adjacent a boundary between first and second cells of the semiconductor device.

Abstract: Semiconductor devices are provided. A semiconductor device includes a gate structure and an adjacent contact. The semiconductor device includes a connector that is connected to the contact. In some embodiments, the semiconductor device includes a wiring pattern that is connected to the connector. Moreover, in some embodiments, the connector is adjacent a boundary between first and second cells of the semiconductor device.

Abstract: A printed circuit board (PCB) is provided as follows. A first connection pad and a second connection pad are disposed on a first surface and a second surface of the base substrate layer, respectively. The first connection pad and the second connection pad each includes a first metal. A first pad cover layer covers a top surface of the first connection pad and includes an insulating metal oxide having a second metal different from the first metal.

Abstract: A semiconductor device includes a substrate including a first region and a second region, a cell gate pattern on the first region of the substrate, a dummy gate pattern on the second region of the substrate, a resistor pattern on the second region of the substrate and over the dummy gate pattern, and a connection structure coupled to each of the connection regions. The resistor pattern includes a body region and connection regions at both sides of the body region. The dummy gate pattern overlaps the body region and does not be overlap the connection regions, when viewed in a plan view.

Abstract: A substrate processing system comprising a polishing part, a pre-cleaning region, and a cleaning part. The polishing part performs a Chemical Mechanical Polishing (CMP) process on a substrate. The pre-cleaning region is prepared in the polishing part and allows pre-cleaning performed on the substrate having undergone the polishing process. The cleaning part cleans the substrate pre-cleaned in the pre-cleaning region.

Abstract: A semiconductor device includes a substrate including a first region and a second region, a cell gate pattern on the first region of the substrate, a dummy gate pattern on the second region of the substrate, a resistor pattern on the second region of the substrate and over the dummy gate pattern, and a connection structure coupled to each of the connection regions. The resistor pattern includes a body region and connection regions at both sides of the body region. The dummy gate pattern overlaps the body region and does not be overlap the connection regions, when viewed in a plan view.

Abstract: Semiconductor devices are provided. A semiconductor device includes a gate structure and an adjacent contact. The semiconductor device includes a connector that is connected to the contact. In some embodiments, the semiconductor device includes a wiring pattern that is connected to the connector. Moreover, in some embodiments, the connector is adjacent a boundary between first and second cells of the semiconductor device.

Abstract: A semiconductor device includes a substrate including a first region and a second region, a cell gate pattern on the first region of the substrate, a dummy gate pattern on the second region of the substrate, a resistor pattern on the second region of the substrate and over the dummy gate pattern, and a connection structure coupled to each of the connection regions. The resistor pattern includes a body region and connection regions at both sides of the body region. The dummy gate pattern overlaps the body region and does not be overlap the connection regions, when viewed in a plan view.

Abstract: Semiconductor devices are provided. A semiconductor device includes a gate structure and an adjacent contact. The semiconductor device includes a connector that is connected to the contact. In some embodiments, the semiconductor device includes a wiring pattern that is connected to the connector. Moreover, in some embodiments, the connector is adjacent a boundary between first and second cells of the semiconductor device.

Abstract: A semiconductor device and a fabricating method thereof are provided. The method includes sequentially forming an interlayer insulating layer and a hard mask layer on a substrate with first and second regions, performing a first patterning process on the hard mask layer to form first openings in the first and second regions, performing a second patterning process on the hard mask layer to form second openings in the first and second regions, and performing a third patterning process on the hard mask layer to selectively form at least one third opening in only the second region. The third patterning process includes forming a first photoresist pattern with openings on the hard mask layer, and the opening of the first photoresist pattern on the first region is overlapped with the second opening on the first region, when viewed in a plan view.

Abstract: Semiconductor devices are provided. A semiconductor device includes a gate structure and an adjacent contact. The semiconductor device includes a connector that is connected to the contact. In some embodiments, the semiconductor device includes a wiring pattern that is connected to the connector. Moreover, in some embodiments, the connector is adjacent a boundary between first and second cells of the semiconductor device.

Abstract: A printed circuit board (PCB) is provided as follows. A first connection pad and a second connection pad are disposed on a first surface and a second surface of the base substrate layer, respectively. The first connection pad and the second connection pad each includes a first metal. A first pad cover layer covers a top surface of the first connection pad and includes an insulating metal oxide having a second metal different from the first metal.

Abstract: A semiconductor device includes a substrate including a first region and a second region, a cell gate pattern on the first region of the substrate, a dummy gate pattern on the second region of the substrate, a resistor pattern on the second region of the substrate and over the dummy gate pattern, and a connection structure coupled to each of the connection regions. The resistor pattern includes a body region and connection regions at both sides of the body region. The dummy gate pattern overlaps the body region and does not be overlap the connection regions, when viewed in a plan view.

Abstract: A semiconductor device and a fabricating method thereof are provided. The method includes sequentially forming an interlayer insulating layer and a hard mask layer on a substrate with first and second regions, performing a first patterning process on the hard mask layer to form first openings in the first and second regions, performing a second patterning process on the hard mask layer to form second openings in the first and second regions, and performing a third patterning process on the hard mask layer to selectively form at least one third opening in only the second region. The third patterning process includes forming a first photoresist pattern with openings on the hard mask layer, and the opening of the first photoresist pattern on the first region is overlapped with the second opening on the first region, when viewed in a plan view.

Abstract: A substrate processing system comprising a polishing part, a pre-cleaning region, and a cleaning part. The polishing part performs a Chemical Mechanical Polishing (CMP) process on a substrate. The pre-cleaning region is prepared in the polishing part and allows pre-cleaning performed on the substrate having undergone the polishing process. The cleaning part cleans the substrate pre-cleaned in the pre-cleaning region.

Abstract: Provided are a substrate cleaning apparatus and method and a brush assembly used therein. The substrate cleaning apparatus for contact-cleaning a substrate includes a cleaning brush rotatably disposed in a cylindrical shape and having an outer circumferential surface contacting the substrate to clean the substrate. Here, the cleaning brush includes a plurality of pressure chambers expanding by a fluid pressure and disposed along a longitudinal direction of a rotation axis rotating at a central portion of the cleaning brush, and the plurality of pressure chambers are individually expandable to allow a portion of the outer circumferential surface to protrude in a radial direction and thus contact-clean a portion of the substrate.

Abstract: The present inventive concept provides a package substrate. The package substrate comprises an insulating substrate having a top surface a circuit pattern disposed on the top surface, and a multilayer conductive joint unit disposed on the circuit pattern. The multilayer conductive joint unit comprises a nickel layer which is in contact with the circuit pattern, and an aluminum layer disposed on the nickel layer and connected to a semiconductor chip mounted on the insulating substrate.

Abstract: A semiconductor device has improved reliability by preventing a fuse cut through a repair process from being electrically reconnected by electrochemical migration. The semiconductor device includes a substrate, a fuse including a first fuse pattern and a second fuse pattern formed at the same level on the substrate, the first fuse pattern and the second fuse pattern being spaced a first width apart from each other such that a gap in the fuse is disposed at a first location between the first fuse pattern and the second fuse pattern, and a first insulation layer formed on the first fuse pattern and the second fuse pattern, the first insulation layer including an opening above the first location and having a second width smaller than the first width.

Abstract: A bump structure may include a body portion spaced apart from a pad disposed on a substrate and a first extension extending from a side of the body portion onto the pad. A second extension extends from another side of the body portion.