Abstract: Under the present invention, a wireless sensor network comprising a plurality of peer to peer nodes is provided. Each node in the network includes, among other things, a sensor for detecting environmental factors. When a potential failure is detected within a node, the node will query its neighboring nodes to determine whether they have the capability to store any data component(s) currently stored within the potentially failing node. Based on the querying, the data component(s) in the potentially failing node are copied to one or more of the neighboring nodes. Thereafter, details of the copying can be broadcast to other nodes in the network, and any routing tables that identify the locations of data components stored throughout the wireless sensor network can be updated.

Abstract: The present invention provides a touch sensor track point (and methods) for a computer such as a laptop or portable device (e.g., PDA, cellular phone, etc.). The touch sensor track point includes a shaft (e.g., typically positioned on a keyboard) and a set (at least one) of directional sensors positioned over a top surface of the shaft. The set of directional sensors can detect manipulations in three dimensions (up-down, left-right, and in-out). In a typical embodiment, the touch sensor track point will cause a computer cursor to move in a direction that corresponds to a location on the set of directional sensors at which a vertical touch is applied. With such a capability, the touch applied to the set of vertical sensors can optionally be substantially horizontally motionless.

Abstract: Specifically, under the present invention an available on-chip memory is coupled to another logic core or memory (e.g., cache) unit using a set of cache managers. Specifically, each cache manager is coupled to the input and output of a cache memory unit. This allows the assigned memory to become an extension of the same level cache, next level cache memory, or memory buffer. This also allows the recovery of a memory block whose logic core is not operational, and is used to improve cache memory performance of the system.

Abstract: Specifically, under the present invention, a cache memory unit can be designated as a pseudo cache memory unit for another cache memory unit within a common hierarchal level. For example, in case of cache miss at cache memory unit “X” on cache level L2 of a hierarchy, a request is sent to a cache memory unit on cache level L3 (external), as well as one or more other cache memory units on cache level L2. The L2 level cache memory units return search results as a hit or a miss. They typically do not search L3 nor write back with the L3 result even (e.g., if it the result is a miss). To this extent, only the immediate origin of the request is written back with L3 results, if all L2s miss.

Abstract: The present invention enables fast transition between sleep and normal modes for circuits such as digital circuits. This invention utilizes chip internal charge transfer operations to put the circuit into fast sleep. The invention reduces external power involvement, and it expedites the sleep mode transition time by limiting charge transfers within the circuit. The fast sleep and fast wake-up enable more efficient power management of the system. This functionality also maximizes performance per power, and provides a more energy efficient computing architecture.

Abstract: This invention describes an apparatus, computer architecture, memory structure, memory control, and cache memory operation method for multi-core processor. A logic core bypasses immediate cache memory units with low yield or deadly performance. The core mounts (multiple) cache unit(s) that might already be in use by other logic cores. Selected cache memory units serve multiple logic cores with the same contents. The shared cache memory unit(s) serves all the mounting cores with cache search, hit, miss, and write back functions. The method recovers a logic core whose cache memory block is not operational by sharing cache memory blocks which might already engage other logic cores. The method is used to improve reliability and performance of the remaining system.

Abstract: This invention describes an apparatus, computer architecture, memory structure, memory control, and cache memory operation method for multi-core processor. A logic core shares requests when faced with immediate cache memory units having low yield or deadly performance. The core mounts (multiple) cache unit(s) that might already be in use by other logic cores. Selected cache memory units serve multiple logic cores with the same contents. The shared cache memory unit(s) serves all the mounting cores with cache search, hit, miss, and write back functions. The method recovers a logic core whose cache memory block is not operational by sharing cache memory blocks which might already engage other logic cores. The method is used to improve reliability and performance of the remaining system.

Abstract: The invention provides a method, system, and program product for authenticating a user to a telephonic communication device. In one embodiment, the invention includes obtaining a reference sample of an authorized user's voice, storing the reference sample of the authorized user's voice, collecting a sample of the voice of a user of the telephonic communication device, comparing the sample of the voice of the user to the reference sample of the authorized user's voice, determining whether the user is the authorized user, and in the case that the user is determined not to be the authorized user, prohibiting use of the telephonic communication device.

Abstract: Among other things, the disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling/main processing elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs using program code embodied as a set of virtualized control threads. The apparatus includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements. In accordance with these features, virtualized control threads can traverse the physical boundaries of the MCP to control SPE(s) (e.g., logical partitions having one or more SPEs) in a different physical partition (e.g., different from the physical partition from which the virtualized control threads originated.

Abstract: This disclosure describes an apparatus, computer architecture, method, operating system, compiler, and application program products for MPEs as well as virtualization across physical boundaries that define physical partitions in a symmetric MCP. Among other things, the disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling/main processing elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). The arrangement also enables MPEs to delegate functionality to one or more groups of SPEs such that those group(s) of SPEs may act as pseudo MPEs. Such delegation may occur across the physical boundaries. Regardless, the pseudo MPEs may utilize pseudo virtualized control threads to control the behavior of other groups of SPEs also across physical boundaries.

Abstract: The disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs using program code embodied as a set of virtualized control threads. The arrangement also enables MPEs delegate functionality to one or more groups of SPEs such that those group(s) of SPEs will act as pseudo MPEs. The pseudo MPEs will utilize pseudo virtualized control threads to control the behavior of other groups of SPEs. In a typical embodiment, the apparatus includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements.

Abstract: This invention describes an apparatus, computer architecture, method, operating system, compiler, and application program products for MPEs as well as virtualization in a symmetric MCP. The disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs. The apparatus enables virtualized control threads within MPEs to be assigned to different groups of SPEs for controlling the same. The apparatus further includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements.

Abstract: Disclosed is a method and apparatus for operating a search system for searching a search space containing domains each representing a collection of related documents. The method includes establishing a domain characterization model (DCM) that includes a DCM index containing keywords and, for each keyword, an identification of a domain where the keyword is found. In response to an original search query, the method forms one or a plurality of enhanced search queries in accordance with the DCM for searching a plurality of domains. Each enhanced search query is formed for searching a particular targeted domain and contains the original search query and at least one keyword associated with the particular domain. The search results are clustered and are displayed so as to be organized by the domains that were searched. The top search results returned in response to each enhanced search query belong to one of the targeted domains.

Abstract: The present invention provides a smart RFID infrastructure and method. Specifically, under the present invention, the infrastructure includes a set (e.g., one or more) of smart RFID tags adapted to communicate with one another, wherein each operating smart RFID tag is adapted to create an individual table of information pertaining to operation of other smart RFID tags. In addition, the infrastructure includes a set of writeable RFID tags adapted to communicate with and receive the individual table of information from each operating smart RFID tag, wherein each of the set of writeable RFID tags is further adapted to create a master table of information based on the individual table of information received from each operating smart RFID tag.

Abstract: This solution relates to machine vision computing environments, and more specifically relates to a system and method for selectively accelerating the execution of image processing applications using a cell computing system. The invention provides a high performance machine vision system over the prior art and provides a method for executing image processing applications on a Cell and BPE3 image processing system. Moreover, implementations of the invention provide a machine vision system and method for distributing and managing the execution of image processing applications at a fine-grained level via a PCIe connected system. The hybrid system is replaced with the BPE3 and the switch is also eliminated from the prior in order to meet over 1 GB processing requirement.

Abstract: A resilient classifier for using with a rule-based system is provided. A system for classifying data for a rule-based system, may include: a system(s) for generating two training data sets, one data set is generated from input data while the second data set is generated from disturbed data; a system for merging the two training data sets; and a system for training a data classifier with the merged training data sets. As a result, the classification of data becomes more accurate, including when disturbed data is encountered.

Abstract: Under the present invention source code can be shared among nodes in a peer-to-peer network. Specifically, source code to be shared will first be analyzed to identify a set of code patterns, assigned one or more predetermined categories based on the set of code patterns, and then selectively indexed. A developer desiring to use previously created source code when creating a new program can perform a context dependent search based on his/her working code to identify and retrieve relevant source code.

Abstract: One or more on-chip VNCAP or MIMCAP capacitors utilize a variable MOS capacitor to improve the uniform capacitance value of the capacitors. This permits the production of silicon semiconductor chips on which are mounted capacitors having capacitive values that are precisely adjusted to be within a range of between about 1% and 5% of their design value. This optimization can be achieved by the use of a back-to-back connection between a pair of the variable MOS capacitors for DC decoupling. It involves the parallelization of on-chip BEOL capacitance of VNCAP and/or MIMCAP capacitors by the insertion in the FEOL of pairs of back-to-back variable MOS capacitors.

Abstract: One or more on-chip VNCAP or MIMCAP capacitors utilize a variable MOS capacitor to improve the uniform capacitance value of the capacitors. This permits the production of silicon semiconductor chips on which are mounted capacitors having capacitive values that are precisely adjusted to be within a range of between about 1% and 5% of their design value. This optimization can be achieved by the use of a back-to-back connection between a pair of the variable MOS capacitors for DC decoupling. It involves the parallelization of on-chip BEOL capacitance of VNCAP and/or MIMCAP capacitors by the insertion in the FEOL of pairs of back-to-back variable MOS capacitors.

Abstract: Under the present invention source code can be shared among nodes in a peer-to-peer network. Specifically, source code to be shared will first be analyzed to identify a set of code patterns, assigned one or more predetermined categories based on the set of code patterns, and then selectively indexed. A developer desiring to use previously created source code when creating a new program can perform a context dependent search based on his/her working code to identify and retrieve relevant source code.